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| DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 1 DM8603-12-ds-p01 november 8, 2010 davicom semiconductor, inc . DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface datasheet preliminary datasheet version: DM8603-ds-p01 november 8, 2010
DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 2 DM8603-12-ds-p01 november 8, 2010 content 1. general desc ription............................................................................................ 8 2. block di agram ........................................................................................................ 8 3. features ................................................................................................................... 9 4. pin config uration ............................................................................................... 10 5. pin descri ption ..................................................................................................... 11 5.1 p2 mii / reduce mii / reverse mii.............................................................................................. .................... 11 5.1.1 mii ............................................................................................................................ ................................. 11 5.1.2 reduce mii..................................................................................................................... ........................... 11 5.1.3 reverse mii.................................................................................................................... ........................... 12 5.2 eeprom interface............................................................................................................... ............................. 12 5.3 led pins ....................................................................................................................... ...................................... 12 5.4 clock int erface ................................................................................................................ ................................... 13 5.5 network interface .............................................................................................................. ................................ 13 5.6 miscellane ous pins............................................................................................................. ................................. 13 5.7 power pins..................................................................................................................... ...................................... 14 5.8 strap pins table ............................................................................................................... .................................. 14 6. phy regis ters ....................................................................................................... 15 6.1 phy registers map.............................................................................................................. .............................. 15 6.2 basic mode control register (040h, 060h)....................................................................................... ................ 16 6.3 basic mode status re gister (041 h, 061h) ........................................................................................ ................. 17 6.4 phy id identifier regi ster 1 (042h, 062h)...................................................................................... ................. 19 6.5 phy id identifier regi ster 2 (043h, 063h)...................................................................................... ................. 19 6.6 auto-negotiation advertisemen t register (044h, 064h) ........................................................................... ....... 20 6.7 auto-negotiation link partner ability register (0 45h, 06 5h).................................................................... .... 21 6.8 auto-negotiation expansio n register (046h, 066h) ............................................................................... .......... 22 6.9 specified configuration register (054h, 074h) .................................................................................. .............. 23 6.10 power saving control register (05dh, 07dh) ..................................................................................... ............ 24 7. switch regis ters................................................................................................. 25 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 3 DM8603-12-ds-p01 november 8, 2010 7.1 switch registers map........................................................................................................... .............................. 25 7.2 per port swit ch register....................................................................................................... ............................. 28 7.2.1 per port status regist er (110h, 13 0h, 150h).................................................................................... ....... 28 7.2.2 per port basic control regi ster 1 (111h, 131h, 151h) ........................................................................... 28 7.2.3 per port basic control regi ster 2 (112h, 132h, 152h) ........................................................................... 30 7.2.4 per port block control regi ster 1 (113h, 133h, 153h)........................................................................... 31 7.2.5 per port block control regi ster 2 (114h, 134h, 154h)........................................................................... 32 7.2.6 per port bandwidth control regi ster (115h, 135h, 155h)..................................................................... 33 7.2.7 per port vlan tag register (116h, 136h, 156h).................................................................................. .35 7.2.8 per port priority & vlan contro l register (117h, 137h, 157h) ......................................................... 35 7.2.9 per port advanced control re gister (119h, 139h, 159h) ...................................................................... 37 7.3 global switch register......................................................................................................... .............................. 38 7.3.1 switch status register (210h) .................................................................................................. ................ 38 7.3.2 switch reset re gister ( 211h)................................................................................................... ................. 38 7.3.3 switch control register (212h)................................................................................................. ............... 39 7.3.4 mirror control register (213h)................................................................................................. .............. 39 7.3.5 special tag ether-ty pe register (214h)......................................................................................... ........ 40 7.3.6 global learning & aging co ntrol register (215h) ............................................................................... 4 0 7.3.7 vlan priority map register (217h).............................................................................................. ......... 41 7.3.8 tos priority map register 1 (218h)............................................................................................. .......... 41 7.3.9 tos priority map register 2 (219h)............................................................................................. .......... 42 7.3.10 tos priority map register 3 (21ah) ............................................................................................. ......... 42 7.3.11 tos priority map register 4 (21bh) ............................................................................................. ......... 43 7.3.12 tos priority map register 5 (21ch) ............................................................................................. ......... 43 7.3.13 tos priority map register 6 (21dh) ............................................................................................. ......... 44 7.3.14 tos priority map register 7 (21eh) ............................................................................................. ......... 44 7.3.15 tos priority map register 8 (21fh) ............................................................................................. ......... 45 7.3.16 mib counter disabl e register (230h)............................................................................................ ......... 46 7.3.17 mib counter contro l register (231h) ............................................................................................ ........ 46 7.3.18 mib counter data register 1 (232h) ............................................................................................. ......... 47 7.3.19 mib counter data register 2 (233h) ............................................................................................. ......... 47 7.3.20 vlan mode & rule cont rol register (23eh) ....................................................................................... 48 7.3.21 vlan table register 0 (270h) ................................................................................................... ............. 50 7.3.22 vlan table register 1 (271h) ................................................................................................... ............. 50 7.3.23 vlan table register 2 (272h) ................................................................................................... ............. 50 7.3.24 vlan table register 3 (273h) ................................................................................................... ............. 50 7.3.25 vlan table register 4 (274h) ................................................................................................... ............. 51 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 4 DM8603-12-ds-p01 november 8, 2010 7.3.26 vlan table register 5 (275h) ................................................................................................... ............. 51 7.3.27 vlan table register 6 (276h) ................................................................................................... ............. 51 7.3.28 vlan table register 7 (277h) ................................................................................................... ............. 51 7.3.29 vlan table register 8 (278h) ................................................................................................... ............. 52 7.3.30 vlan table register 9 (279h) ................................................................................................... ............. 52 7.3.31 vlan table register 10 (27ah) .................................................................................................. ........... 52 7.3.32 vlan table regi ster 11 (27bh).................................................................................................. ............ 52 7.3.33 vlan table register 12 (27ch) .................................................................................................. ........... 53 7.3.34 vlan table register 13 (27dh) .................................................................................................. ........... 53 7.3.35 vlan table regi ster 14 (27eh).................................................................................................. ............ 53 7.3.36 vlan table register 15 (27fh).................................................................................................. ............ 53 7.3.37 stp control re gister (292h).................................................................................................... ................ 54 7.3.38 snooping control re gister 1 (29bh) ............................................................................................. .......... 54 7.3.39 snooping control re gister 2 (29ch) ............................................................................................. .......... 55 7.3.40 address table control & st atus register (2b0h)................................................................................. .56 7.3.41 address table data register 1 (2b1h)........................................................................................... ......... 57 7.3.42 address table data register 2 (2b2h)........................................................................................... ......... 57 7.3.43 address table data register 3 (2b3h)........................................................................................... ......... 57 7.3.44 address table data register 4 (2b4h)........................................................................................... ......... 57 7.3.45 address table data 4 register (2b5h)........................................................................................... ......... 57 7.3.46 vendor id register (310h) ...................................................................................................... ................. 57 7.3.47 product id register (311h) ..................................................................................................... ................. 58 7.3.48 port 2 mac contro l register (315h) ............................................................................................. ......... 59 7.3.49 eeprom control & address register (31ah) ..................................................................................... 60 7.3.50 eeprom data register (31bh) .................................................................................................... .......... 60 7.3.51 strap pin control & st atus regist er (31ch) ..................................................................................... ..... 61 7.3.52 smi bus error chec k register (339h)............................................................................................ ........ 62 7.3.53 smi bus control register (33ah) ................................................................................................ ........... 62 7.3.54 phy control register (33eh) .................................................................................................... .............. 63 8. eeprom fo rmat ..................................................................................................... 64 9. functional de scription.................................................................................... 69 9.1 host serial management interface ............................................................................................... .................... 69 9.1.1 host smi fra me structure ....................................................................................................... ............... 69 9.1.2 host smi bus error check function .............................................................................................. ....... 70 9.2 switch functions ............................................................................................................... ................................. 71 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 5 DM8603-12-ds-p01 november 8, 2010 9.2.1 address learning............................................................................................................... ....................... 71 9.2.2 address aging .................................................................................................................. ......................... 71 9.2.3 packet fo rwarding .............................................................................................................. ..................... 71 9.2.4 inter-packet gap (ipg)......................................................................................................... ................... 71 9.2.5 back-off al gorithm............................................................................................................. ...................... 71 9.2.6 late co llision ................................................................................................................. ........................... 72 9.2.7 full duplex fl ow control....................................................................................................... .................. 72 9.2.8 half duplex flow control....................................................................................................... ................. 72 9.2.9 partition mode ................................................................................................................. ......................... 72 9.2.10 broadcast sto rm filt ering...................................................................................................... .................. 73 9.2.11 bandwidth control .............................................................................................................. ..................... 73 9.2.12 port monitoring support ........................................................................................................ ................. 73 9.2.13 vlan support ................................................................................................................... ....................... 74 9.2.13.1 port-based vlan .............................................................................................................. 74 9.2.13.2 802.1q-based vlan .......................................................................................................... 74 9.2.13.3 tag/untag...................................................................................................................... ..... 74 9.2.14 special tag .................................................................................................................... ............................ 75 9.2.15 priority support............................................................................................................... ......................... 77 9.2.15.1 port-based priority ........................................................................................................... 7 7 9.2.15.2 802.1p-based pr iority ....................................................................................................... 77 9.2.15.3 diffserv-based priority..................................................................................................... 77 9.2.16 address tabl e accessing ........................................................................................................ .................. 78 9.2.16.1 type of addr ess tabl e...................................................................................................... 78 9.2.16.2 access rules of ad dress table ...................................................................................... 78 9.2.17 igmp snooping .................................................................................................................. ...................... 82 9.2.18 ipv6 mld snooping .............................................................................................................. ................... 82 9.2.19 stp / rstp support............................................................................................................. .................... 83 9.3 mii interface .................................................................................................................. .................................... 86 9.3.1 mii data interface............................................................................................................. ....................... 86 9.3.2 mii serial management interface................................................................................................ ........... 87 9.4 internal phy functions......................................................................................................... ............................ 88 9.4.1 100base-tx operati on ........................................................................................................... .................. 88 9.4.1.1 4b5b encoder................................................................................................................... .88 9.4.1.2 scrambler...................................................................................................................... ..... 88 9.4.1.3 parallel to serial conver ter .............................................................................................. 88 9.4.1.4 nrz to nrzi encode r........................................................................................................ 88 9.4.1.5 mlt-3 conv erter................................................................................................................ 88 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 6 DM8603-12-ds-p01 november 8, 2010 9.4.1.6 mlt-3 dr iver ................................................................................................................... ... 89 9.4.1.7 4b5b code group ............................................................................................................. 90 9.4.2 100base-tx receiver............................................................................................................ .................... 91 9.4.2.1 signal detect .................................................................................................................. ... 91 9.4.2.2 adaptive equa lization....................................................................................................... 91 9.4.2.3 mlt-3 to nrzi decoder .................................................................................................... 91 9.4.2.4 clock recovery module.................................................................................................... 91 9.4.2.5 nrzi to nrz .................................................................................................................... ... 92 9.4.2.6 serial to parallel ............................................................................................................. ... 92 9.4.2.7 descrambler .................................................................................................................... .. 92 9.4.2.8 code group a lignment..................................................................................................... 92 9.4.2.9 4b5b decoder................................................................................................................... .92 9.4.3 10base-t operation............................................................................................................. ..................... 93 9.4.4 collision de tection ............................................................................................................ ........................ 93 9.4.5 carrier sense.................................................................................................................. ........................... 93 9.4.6 auto-negotiation............................................................................................................... ........................ 93 9.5 lfp and fef function ........................................................................................................... ........................... 94 9.6 hp auto-mdix function .......................................................................................................... ........................ 94 10. dc and ac electrical characteris tics...................................................... 95 10.1 absolute maxi mum ratings ....................................................................................................... ....................... 95 10.2 operating co nditions........................................................................................................... .............................. 95 10.3 dc electrical ch aracteristics.................................................................................................. .......................... 96 10.4 ac characteristics ............................................................................................................. ................................ 97 10.4.1 power on re set timing .......................................................................................................... ................. 97 10.4.2 port 2 mii interfac e transmit timing ........................................................................................... ........ 98 10.4.3 port 2 mii interfac e receive timing ............................................................................................ .......... 98 10.4.4 port 2 rmii interfa ce transmit timing .......................................................................................... ...... 99 10.4.5 port 2 rmii interf ace receive timing ........................................................................................... ........ 99 10.4.6 mii management interface timing ................................................................................................ ...... 100 10.4.7 host smi inte rface ti ming...................................................................................................... .............. 100 10.4.8 eeprom ti ming .................................................................................................................. ................. 101 11. application in formation ................................................................................ 102 11.1 application of reverse mii ..................................................................................................... ........................ 102 11.2 application of re duce mii to phy ............................................................................................... ................. 103 11.3 application of re duce mii to mac ............................................................................................... ................ 103 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 7 DM8603-12-ds-p01 november 8, 2010 12. package info rmation ...................................................................................... 104 13. terminol ogy........................................................................................................ 105 14. ordering info rmation ..................................................................................... 107 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 8 DM8603-12-ds-p01 november 8, 2010 1. general description the DM8603 is davicom?s new fully integrated three-port 10m/100mbps fast ethernet controller. as a fast ethernet switch, the DM8603 consists of two phy ports and a third port with either mii or rmii interface. as the DM8603 was designed with our customers? requirements in mind, the switch is optimized for high performance while being highly cost-effective. the two phy ports on the DM8603 are ieee 802.3u standards compliant. aside for the first two phy ports and in an effort for maximum application flexibility, the third port on the DM8603 offers the options to either connect with an mii, reversed mii, or rmii. the reversed mii configuration is used to connect with soc?s with a mii interface. the rmii interface is the alternative interface configuration in case of the need to connect a lower pin count ethernet phy or soc. to maximize the performance of each port, the DM8603 was designed with a number of features. for proper bandwidth, each port also supports ingress and/or egress rate control. in support of efficient packet forwarding, the DM8603 has port-based vlan with tag/un-tag functions for up to 16 groups of 802.1q. each port includes mib counters, loop-back capability, built in memory self test (bist) for the system, and board level diagnostic. in designing for the requirements of various data, voice, and video applications, enough internal memory has been provided for usage of the DM8603?s three ports, and the internal memory supports up to 1k uni-cast mac address table. then to meet the demands of various bandwidth and latency issues in data, voice, and video applications, each port of the DM8603 has four priority transmit queues. these queues can be defined either through port-based operation, 802.1p vlan, or the ip packet tos field automatically. 2. block diagram 10/100m phy port 0 mdi / mdix port 1 mdi / mdix port 2 mii / rmii switch controller control registers mib counters eeprom interface embedded memory memory bist memory management switch engine led control leds eeprom switch fabric smi i/f 10/100m phy 10/100m mac 10/100m mac 10/100m mac DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 9 DM8603-12-ds-p01 november 8, 2010 3. features ? ieee 802.3/u 10base-t/100base-tx compatible ? ethernet switch ports: o two 10/100mbps phy o one mii/rmii interface with reversed - mii support ? supports auto crossover function - hp auto-mdix ? flow control o supports ieee 802.3x flow control in full-duplex mode o supports back pressure flow control in half-duplex mode ? per port support bandwidth, ingress and egress rate control ? per port support priority queues o each port with four queues o port-based, 802.1p vlan, or ip tos priority ? supports 802.1q vlan for up-to 16 vlan groups ? supports vlan id tag/untag options ? supports special tag and double tag header ? supports up-to 1k unicast/multicast shared mac addresses ? supports store and forward switching approach ? supports broadcast storming filter function ? supports serial data management interface ? automatic aging scheme ? supports mib counters for diagnostic ? supports lfp (link fault pass-through) and fef (far end fault) ? supports hardware-based igmp v1,v2 snooping ? supports hardware-based mld v1 snooping ? supports ieee 802.1d stp (spanning tree protocol) and ieee 802.1w rstp (rapid spanning tree protocol) ? eeprom interface o power up configurations o 93c46 or 93c56 auto detection ? package o 64-pin lqfp ? power o 1.8v/3.3v dual power o 3.3v i/o with 5v tolerance DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 10 DM8603-12-ds-p01 november 8, 2010 4. pin configuration 64 pin lqfp: DM8603ep DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 11 DM8603-12-ds-p01 november 8, 2010 5. pin description i = input, o = output, i/o = input / output, o/d = open drain, p = power, # = asserted low pd=internal pull-low (about 50k ohm) 5.1 p2 mii / reduce mii / reverse mii 5.1.1 mii pin no. pin name i/o description 2 phy_mdc o,pd mii serial management data clock 3 phy_mdio i/o mii serial management data 5 6 7 9 p2_txd3 p2_txd2 p2_txd1 p2_txd0 o,pd port 2 mii transmit data 4-bit nibble data outputs (synchronous to the p2_txc) 10 p2_txe o,pd port 2 mii transmit enable 12 p2_txc i/o port 2 mii transmit clock 14 p2_txer o,pd port 2 mii transmit error 15 p2_crs i/o port 2 mii carrier sense 17 p2_col i/o port 2 mii collision detect 18 p2_rxer i port 2 mii receive error 19 p2_rxc i port 2 mii receive clock 20 p2_rxdv i port 2 mii receive data valid 21 22 24 25 p2_rxd3 p2_rxd2 p2_rxd1 p2_rxd0 i port 2 mii receive data 4-bit nibble data input (synchronous to p2_rxc) 5.1.2 reduce mii pin no. pin name i/o description 2 phy_mdc o,pd mii serial management data clock 3 phy_mdio i/o mii serial management data 5 6 p2_txd3 p2_txd2 o,pd not used 7 9 p2_txd1 p2_txd0 o,pd port 2 rmii transmit data 10 p2_txe o,pd port 2 rmii transmit enable 12 p2_txc o 50mhz clock output 14 p2_txer o not used 15 p2_crs i port 2 rmii crs_dv 17 p2_col i not used, tie to ground in application 18 p2_rxer i not used, tie to ground in application 19 p2_rxc i port 2 rmii 50mhz reference clock input 20 p2_rxdv i not used, tie to ground in application 21 22 p2_rxd3 p2_rxd2 i not used, tie to ground in application 24 25 p2_rxd1 p2_rxd0 i port 2 rmii receive data DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 12 DM8603-12-ds-p01 november 8, 2010 5.1.3 reverse mii pin no. pin name i/o description 2 phy_mdc o,pd not used 3 phy_mdio i/o not used 5 6 7 9 p2_txd3 p2_txd2 p2_txd1 p2_txd0 o,pd port 2 revmii transmit data 4-bit nibble data outputs (synchronous to the p2_txc) 10 p2_txe o,pd port 2 revmii transmit enable 12 p2_txc o port 2 revmii transmit clock 14 p2_txer o,pd port 2 revmii transmit error 15 p2_crs o port 2 revmii carrier sense output when p2_txe or p2_rxdv are asserted 17 p2_col o port 2 revmii collision output when p2_txe and p2_rxdv are asserted 18 p2_rxer i port 2 revmii receive error 19 p2_rxc i port 2 revmii receive clock 20 p2_rxdv i port 2 revmii receive data valid 21 22 24 25 p2_rxd3 p2_rxd2 p2_rxd1 p2_rxd0 i port 2 revmii receive data 4-bit nibble data input (synchronous to p2_rxc) 5.2 eeprom interface pin no. pin name i/o description 27 eedio i/o eeprom data in/out 28 eeck o,pd eeprom serial clock this pin is used as the clock for the eeprom data transfer 29 eecs o,pd eeprom chip selection 5.3 led pins pin no. pin name i/o description 55 p1_lnk_led o port 1 link / active led it is the combined led of link and carrier sense signal of the internal phy1 56 p1_spd_led o port 1 speed led its low output indicates that the internal phy1 is operated in 100m/s, or it is floating for the 10m mode of the internal phy1 57 p0_lnk_led o port 0 link / active led it is the combined led of link and carrier sense signal of the internal phy0 58 p0_spd_led o port 0 speed led its low output indicates that the internal phy0 is operated in 100m/s, or it is floating for the 10m mode of the internal phy0 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 13 DM8603-12-ds-p01 november 8, 2010 5.4 clock interface pin no. pin name i/o description 52 x1 i crystal or osc 25mhz input 53 x2 o crystal 25mhz output 5.5 network interface pin no. pin name i/o description 34 35 p1_tx+ p1_tx - i/o port 1 tp tx these two pins are the twisted pair transmit in mdi mode or receive in mdix mode 37 38 p1_rx+ p1_rx- i/o port 1 tp rx these two pins are the twisted pair receive in mdi mode or transmit in mdix mode 41 42 p0_tx+ p0_tx- i/o port 0 tp tx these two pins are the twisted pair transmit in mdi mode or receive in mdix mode 44 45 p0_rx+ p0_rx - i/o port 0 tp rx these two pins are the twisted pair receive in mdi mode or transmit in mdix mode 47 bgres i/o band-gap pin connect a 6.8k1% ohm resistor to bggnd in application 48 bggnd p band-gap ground 49 vcntl i/o 1.8v voltage control 50 vref o voltage reference connect a 0.1uf capacitor to ground in application 5.6 miscellaneous pins pin no. pin name i/o description 30 pwrst# i power on reset low active with minimum 1ms 60 smi_mdc i serial data management interface clock 62 smi_mdio i/o serial data management interface data in/out 32 test1 i,pd test pin 1 tie to dvdd33 in application 59 test2 i,pd test pin 2 tie to dvdd33 in application 63 test3 i,pd test pin 3 tie to dvdd33 in application DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 14 DM8603-12-ds-p01 november 8, 2010 5.7 power pins pin no. pin name i/o description 1,13,26,51 dvdd33 p digital 3.3v power 11,61 dvdd18 p digital 1.8v power 4,8,16,23,31,64 dgnd p digital gnd 39,46 avdd33 p analog 3.3v power 33,40 avdd18 p analog 1.8v power 36,43,54 agnd p analog gnd 5.8 strap pins table pin no. pin name description 10 p2_txe port 2 force mode enable 0: port 2 is normal mode 1: port 2 is force mode 28 eeck port 2 speed selection in force mode 0: port 2 is forced in 10 mbps mode 1: port 2 is forced in 100 mbps mode 29 eecs port 0 fiber mode enable 0: port 0 is tp mode 1: port 0 is fiber mode 14 p2_txer port 1 fiber mode enable 0: port 1 is tp mode 1: port 1 is fiber mode 5 6 p2_txd3 p2_txd2 p2 mode configuration p2_txd3 p2_txd2 0 0 port 2 is mii mode 0 1 port 2 is reverse mii mode 1 0 port 2 is rmii mode 1 1 lfp function is enabled (port 2 is mii mode) note: 1 = external pull-high with resistor 1k~10k ohm 0 = internal pull-low (default) or external pull-low DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 15 DM8603-12-ds-p01 november 8, 2010 6. phy registers 6.1 phy registers map phy_adr reg_adr abs_adr register description default 02h 00h 040h port 0 phy basic mode control register 3100h 01h 041h port 0 phy basic mode status register 7849h 02h 042h port 0 phy identifier 1 register 0181h 03h 043h port 0 phy identifier 2 register b8b0h 04h 044h port 0 phy auto-negotiation advertisement register 01e1h 05h 045h port 0 phy auto-negotiation link partner ability register 0000h 06h 046h port 0 phy auto-negotiation expansion register 0000h 14h 054h port 0 phy specifie d configuration register - 1dh 05dh port 0 phy power saving control register 0000h 03h 00h 060h port 1 phy basic mode control register 3100h 01h 061h port 1 phy basic mode status register 7849h 02h 062h port 1 phy identifier 1 register 0181h 03h 063h port 1 phy identifier 2 register b8b0h 04h 064h port 1 phy auto-negotiation advertisement register 01e1h 05h 065h port 1 phy auto-negotiation link partner ability register 0000h 06h 066h port 1 phy auto-negotiation expansion register 0000h 14h 074h port 1 phy specifie d configuration register - 1dh 07dh port 1 phy power saving control register 0000h note: phy_adr = DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 16 DM8603-12-ds-p01 november 8, 2010 6.2 basic mode control register (040h, 060h) phy_adr reg_adr abs_adr 02h, 03h 00h 040, 060h bit bit name default description 15 reset rw/sc 0b reset this bit sets the status and controls the phy registers to their default states. this bit, which is self-clear ing, will keep returning a value of one until the reset process is completed 1 = software reset 0 = normal operation 14 loopback rw 0b loopback loop-back control register. when in 100mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" bef ore any valid data appears at the mii receive outputs 1 = loop-back enabled 0 = normal operation 13 speed selection rw 1b speed select link speed may be selected either by this bit or by auto-negotiation. when auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 1 = 100mbps 0 = 10mbps 12 auto-negotiation enable rw 1b auto-negotiation enable 1 = auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 0 = auto-negotiation is disabled. 11 power down rw 0b power down while in the power-down state, the phy should respond to management transactions. during the transition to power-down state and while in the power-down state, the phy should not generate spurious signals on the mii 1 = power down 0 = normal operation 10 isolate rw 0b isolate force to 0 in application. 9 restart auto-negotiation rw/sc 0b restart auto-negotiation re-initiates the auto-negotiation process. when auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. this bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM8603. the operation of the auto-ne gotiation process will not be affected by the management entity that clears this bit 1 = restart auto-negotiation. 0 = normal operation 8 duplex mode rw 1b duplex mode duplex selection is allowed when auto-negotiation is disabled (bit 12 of this register is cleared). with auto-negotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 1 = full duplex operation. 0 = normal operation DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 17 DM8603-12-ds-p01 november 8, 2010 7 collision test rw 0b collision test when set, this bit will cause the col signal to be asserted in response to the assertion of tx _en in internal mii interface. 1 = collision test enabled. 0 = normal operation 6:0 reserved ro 0h reserved write as 0h, ignore when read 6.3 basic mode status register (041h, 061h) phy_adr reg_adr abs_adr 02h, 03h 01h 041, 061h bit bit name default description 15 100base-t4 ro/p 0b 100base-t4 capable 1 = DM8603 is able to perform in 100base-t4 mode 0 = DM8603 is not able to perform in 100base-t4 mode 14 100base-tx full-duplex ro/p 1b 100base-tx full duplex capable 1 = DM8603 is able to perform 100base-tx in full duplex mode 0 = DM8603 is not able to perform 100base-tx in full duplex mode 13 100base-tx half-duplex ro/p 1b 100base-tx half duplex capable 1 = DM8603 is able to perform 100base-tx in half duplex mode 0 = DM8603 is not able to perform 100base-tx in half duplex mode 12 10base-t full-duplex ro/p 1b 10base-t full duplex capable 1 = DM8603 is able to perform 10base-t in full duplex mode 0 = DM8603 is not able to per form 10base-tx in full duplex mode 11 10base-t half-duplex ro/p 1b 10base-t half duplex capable 1 = DM8603 is able to perform 10base-t in half duplex mode 0 = DM8603 is not able to perform 10base-t in half duplex mode 10:7 reserved ro 0h reserved write as 0h, ignore when read 6 mf preamble suppression ro 1b mii frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed 5 auto-negotiation complete ro 0b auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 4 remote fault ro 0b remote fault 1 = remote fault condition detected (cleared on read or by a chip reset). fault criteria and detection method is DM8603 implementation specific. this bit will set after the rf bit in the anlpar (reg 02h/03h.05h.[13]) is set 0 = no remote fault condition detected 3 auto-negotiation ability ro/p 1b auto configuration ability 1 = DM8603 is able to perform auto-negotiation 0 = DM8603 is not able to perform auto-negotiation 2 link status ro 0b link status the link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 18 DM8603-12-ds-p01 november 8, 2010 cleared and remain cleared until it is read via the management interface. 1 = valid link is established (for either 10mbps or 100mbps operation) 0 = link is not established 1 jabber detect ro 0b jabber detect this bit is implemented with a latc hing function. jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM8603 reset. this bit works only in 10mbps mode 1 = jabber condition detected 0 = no jabber 0 extended capability ro/p 1b extended capability 1 = extended register capable 0 = basic register capable only DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 19 DM8603-12-ds-p01 november 8, 2010 6.4 phy id identifier register 1 (042h, 062h) phy_adr reg_adr abs_adr 02h, 03h 02h 042h, 062h bit bit name default description 15:0 oui_msb ro 0181h oui most significant bits this register stores bit 3 to 18 of the oui (00606e) to bit 15 to 0 of this register respectively. the most significant two bits of the oui are ignored (the ieee standard refers to these as bit 1 and 2) the phy identifier registers #1 and #2 work together in a single identifier of the DM8603. the identifier consists of a concatenation of the organizationally unique identifier (oui), a vendor's model number, and a model revision number. davicom semico nductor's ieee assign ed oui is 00606e. 6.5 phy id identifier register 2 (043h, 063h) phy_adr reg_adr abs_adr 02h, 03h 03h 043h, 063h bit bit name default description 15:10 oui_lsb ro/p 101110b oui least significant bits bit 19 to 24 of the oui (00606e) are mapped to bit 15 to 10 of this register respectively 9:4 vndr_mdl ro/p 001011b vendor model number five bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3:0 mdl_rev ro/p 0001b model revision number five bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 4) DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 20 DM8603-12-ds-p01 november 8, 2010 6.6 auto-negotiation advertisement register (044h, 064h) phy_adr reg_adr abs_adr 02h, 03h 04h 044h, 064h bit bit name default description 15 np ro/p 0b next page indication the DM8603 has no next page, so this bit is permanently set to 0. 0 = no next page available 1 = next page available 14 ack ro 0b acknowledge the DM8603's auto-negot iation state machine will automatically control this bit in the outgoing flp bursts and set it at the appropriate time during the auto-negotiation process. software should not attempt to write to this bit. 1 = link partner ability data reception acknowledged 0 = not acknowledged 13 rf rw 0b remote fault 1 = local device senses a fault condition 0 = no fault detected 12:11 reserved rw 00b reserved write as 00b, ignore when read 10 fcs rw 0b flow control support 1 = controller chip s upports flow control ability 0 = controller chip doesn?t support flow control ability 9 t4 ro/p 0b 100base-t4 support the DM8603 does not support 100base-t4 so this bit is permanently set to 0 1 = 100base-t4 is supported by the local device 0 = 100base-t4 is not supported 8 tx_fdx rw 1b 100base-tx full duplex support 1 = 100base-tx full duplex is supported by t he local device 0 = 100base-tx full duplex is not supported 7 tx_hdx rw 1b 100base-tx support 1 = 100base-tx half duplex is supported by the local device 0 = 100base-tx half duplex is not supported 6 10_fdx rw 1b 10base-t full duplex support 1 = 10base-t full duplex is s upported by the local device 0 = 10base-t full duplex is not supported 5 10_hdx rw 1b 10base-t support 1 = 10base-t half duplex is supported by the local device 0 = 10base-t half duplex is not supported 4:0 selector rw 00001b protocol selection bits these bits contain the binary encode d protocol selector supported by this node <00001> indicates that this device suppor ts ieee 802.3 csma/cd DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 21 DM8603-12-ds-p01 november 8, 2010 6.7 auto-negotiation link partner ability register (045h, 065h) phy_adr reg_adr abs_adr 02h, 03h 05h 045h, 065h bit bit name default description 15 np ro 0b next page indication 0 = link partner, no next page available 1 = link partner, next page available 14 ack ro 0b acknowledge the DM8603's auto-negot iation state machine will automatically control this bit from the incomi ng flp bursts. software should not attempt to write to this bit 1 = link partner ability data reception acknowledged 0 = not acknowledged 13 rf ro 0b remote fault 1 = remote fault indicated by link partner 0 = no remote fault indicated by link partner 12:11 reserved ro 00b reserved write as 00b, ignore when read 10 fcs ro 0b flow control support 1 = controller chip supports fl ow control ability by link partner 0 = controller chip doesn?t support flow control ability by link partner 9 t4 ro 0b 100base-t4 support 1 = 100base-t4 is suppor ted by the link partner 0 = 100base-t4 is not supported by the link partner 8 tx_fdx ro 0b 100base-tx full duplex support 1 = 100base-tx full duplex is supported by t he link partner 0 = 100base-tx full duplex is not supported by t he link partner 7 tx_hdx ro 0b 100base-tx support 1 = 100base-tx half duplex is s upported by the link partner 0 = 100base-tx half duplex is not supported by t he link partner 6 10_fdx ro 0b 10base-t full duplex support 1 = 10base-t full duplex is s upported by the link partner 0 = 10base-t full duplex is not supported by t he link partner 5 10_hdx ro 0b 10base-t support 1 = 10base-t half duplex is supported by the link partner 0 = 10base-t half duplex is not supported by t he link partner 4:0 selector ro 0h protocol selection bits link partner?s binary encoded protocol selector DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 22 DM8603-12-ds-p01 november 8, 2010 6.8 auto-negotiation expansion register (046h, 066h) phy_adr reg_adr abs_adr 02h, 03h 06h 046h, 066h bit bit name default description 15:5 reserved ro 0h reserved write as 0h, ignore when read 4 pdf ro/lh 0b local device parallel detection fault 1 = a fault detected via parallel detection function. 0 = no fault detected via parallel detection function 3 lp_np_able ro 0b link partner next page ability 1 = link partner, next page available 0 = link partner, no next page 2 np_able ro/p 0b local device next page ability DM8603 does not support this function, so this bit is always 0 1 page_rx ro 0b new page received a new link code word p age received. this bit will be automatically cleared when the register (register 6) is read by management 0 lp_an_able ro 0b link partner auto-negotiation ability a ?1? in this bit indicates that the link partner supports auto-negotiation DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 23 DM8603-12-ds-p01 november 8, 2010 6.9 specified configuration register (054h, 074h) phy_adr reg_adr abs_adr 02h, 03h 14h 054h, 074h bit bit name default description 15:12 reserved rw 0000b reserved write as 0000b, ignore when read 11 preamblex rw 0b preamble saving control 0 = when bit 10 is set, the 10 base-t transmit preamble count is reduced. when reg 02h/03h.1dh.[11] is set, 12-bit preamble is reduced; otherwise 22-bit preamble is reduced. 1 = transmit preamble bit count is normal in 10base-t mode 10 tx10m_pwr rw 0b 10base-t mode transmit power saving control 1 = enable transmit power saving in 10base-t mode 0 = disable transmit power saving in 10base-t mode 9 nway_pwr rw 0b auto-negotiation power saving control 1 = disable power saving during auto-negotiation period 0 = enable power saving during auto-negotiation period 8 reserved ro 0b reserved read as 0, ignore on write 7 mdix_cntl ro * the polarity of mdi/mdix value 1 = mdix mode 0 = mdi mode 6 reserved rw 0b reserved write as 0b, ignore when read 5 mdix_fix value rw 0b mdix_cntl force value: when mdix_down = 1, mdix_cntl value depend on the register value 4 mdix_down rw 0b mdix down manual force mdi/mdix. mdix_cntl value depend on reg 02h/03h.14h.[5] 0 = enable hp auto-mdix 1 = disable hp auto-mdix 3:0 reserved rw 0000b reserved write as 0000b, ignore when read DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 24 DM8603-12-ds-p01 november 8, 2010 6.10 power saving control register (05dh, 07dh) phy_adr reg_adr abs_adr 02h, 03h 1dh 05dh, 07dh bit bit name default description 15:12 reserved ro 0000b reserved write as 0000b, ignore when read 11 preamblex rw 0b preamble saving control when both bit reg 02h/03h.14h.[11:10] are set, the 10base-t transmit preamble count is reduced. 1 = 12-bit preamble is reduced. 0 = 22-bit preamble is reduced. 10 reserved rw 0b reserved write as 0b, ignore when read 9 tx_pwr rw 0b transmit power saving control disabled 1 = when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0 = disable transmit driving power saving function 8:0 reserved ro 0h reserved write as 0h, ignore when read DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 25 DM8603-12-ds-p01 november 8, 2010 7. switch registers 7.1 switch registers map phy_adr reg_adr abs_adr register description default 08h 00h~0fh 100h~10fh reserved - 10h 110h port 0 status register - 11h 111h port 0 basic control register 1 0000h 12h 112h port 0 basic control register 2 0000h 13h 113h port 0 block control register 1 0000h 14h 114h port 0 block control register 2 0000h 15h 115h port 0 bandwidth control register 0000h 16h 116h port 0 vlan tag register 0001h 17h 117h port 0 priority & vlan control register 0000h 18h 118h reserved - 19h 119h port 0 advanced control register 0000h 1ah~1fh 11ah~11fh reserved - 09h 00h~0fh 120~12f reserved - 10h 130h port 1 status register 0000h 11h 131h port 1 basic control register 1 0000h 12h 132h port 1 basic control register 2 0000h 13h 133h port 1 block control register 1 0000h 14h 134h port 1 block control register 2 0000h 15h 135h port 1 bandwidth control register 0001h 16h 136h port 1 vlan tag register 0000h 17h 137h port 1 priority & vlan control register - 18h 138h reserved 0000h 19h 139h port 1 advanced control register 093ah 1ah~1fh 13ah~13fh reserved - 0ah 00h~0fh 140h~14fh reserved - 10h 150h port 2 status register 0000h 11h 151h port 2 basic control register 1 0000h 12h 152h port 2 basic control register 2 0000h 13h 153h port 2 block control register 1 0000h 14h 154h port 2 block control register 2 0000h 15h 155h port 2 bandwidth control register 0001h 16h 156h port 2 vlan tag register 0000h 17h 157h port 2 priority & vlan control register - 18h 158h reserved 0000h 19h 159h port 2 advanced control register 093ah 1ah~1fh 15ah~15fh reserved - 10h 00h~0fh 200h~20fh reserved - 10h 210h switch status register - 11h 211h switch reset register 0000h 12h 212h switch control register 0000h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 26 DM8603-12-ds-p01 november 8, 2010 13h 213h mirror control register 0000h 14h 214h special tag ether-type register 8606h 15h 215h global learning & aging control register 0000h 16h 216h reserved - 17h 217h vlan priority map register fa50h 18h 218h tos priority map register 1 fa50h 19h 219h tos priority map register 2 0000h 1ah 21ah tos priority map register 3 5555h 1bh 21bh tos priority map register 4 5555h 1ch 21ch tos priority map register 5 aaaah 1dh 21dh tos priority map register 6 aaaah 1eh 21eh tos priority map register 7 ffffh 1fh 21fh tos priority map register 8 ffffh 11h 00h~0fh 220h~22fh reserved 10h 230h mib counter disable register 0000h 11h 231h mib counter control register 0000h 12h 232h mib counter data register 1 0000h 13h 233h mib counter data register 2 0000h 14h~1dh 234h~23dh reserved - 1eh 23eh vlan mode & rule control register 0000h 1fh 23fh reserved - 13h 00h~0fh 260h~26fh reserved - 10h 270h vlan table register 0 0007h 11h 271h vlan table register 1 0007h 12h 272h vlan table register 2 0007h 13h 273h vlan table register 3 0007h 14h 274h vlan table register 4 0007h 15h 275h vlan table register 5 0007h 16h 276h vlan table register 6 0007h 17h 277h vlan table register 7 0007h 18h 278h vlan table register 8 0007h 19h 279h vlan table register 9 0007h 1ah 27ah vlan table register 10 0007h 1bh 27bh vlan table register 11 0007h 1ch 27ch vlan table register 12 0007h 1dh 27dh vlan table register 13 0007h 1eh 27eh vlan table register 14 0007h 1fh 27fh vlan table register 15 0007h 14h 00h~11h 280h~291h reserved - 12h 292h stp control register 0000h 13h~1ah 293h~29ah reserved - 1bh 29bh snooping control register 1 0700h 1ch 29ch snooping control register 2 097dh 1dh~1fh 29dh~29fh reserved - 15h 00h~0fh 2a0h~2afh reserved - DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 27 DM8603-12-ds-p01 november 8, 2010 10h 2b0h address table control & status register 0000h 11h 2b1h address table data register 1 0000h 12h 2b2h address table data register 2 0000h 13h 2b3h address table data register 3 0000h 14h 2b4h address table data register 4 0000h 15h 2b5h address table data register 5 0000h 16h~1fh 2b6h~2bfh reserved - 18h 00h~0fh 300h~30fh reserved - 10h 310h vendor id register 0a46h 11h 311h product id register 8603h 12h~14h 312h~314h reserved - 15h 315h port 2 mac control register 0100h 16h~19h 316h~319h reserved - 1ah 31ah eeprom control & address register 0040h 1bh 31bh eeprom data register 0000h 1ch 31ch strap pin control & status register - 1dh~1fh 31dh~31fh reserved - 19h 00h~0fh 320h~32fh reserved - 10h~18h 330h~338h reserved - 19h 339h smi bus error check register 0000h 1ah 33ah smi bus control register 0000h 1bh~1dh 33bh~33dh reserved - 1eh 33eh phy control register 0003h 1fh 33fh reserved - 1ch 00h~1fh 380h~39fh reserved - key to default in the register description that follow s, the default column takes the form: DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 28 DM8603-12-ds-p01 november 8, 2010 7.2 per port switch register 7.2.1 per port status register (110h, 130h, 150h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 10h 110h, 130h, 150h bit rom type default description 15:5 --- ro 0h reserved write as 0h, ignore when read 4 --- p, ro * lp_fcs link partner flow control support status 0: link partner don't su pport ieee 802.3x flow control 1: link partner support ieee 802.3x flow control 3 --- ro 0b reserved write as 0b, ignore when read 2 --- p, ro * speed port speed status 0: 10mbps 1: 100mbps 1 --- p, ro * fdx port duplex status 0: half-duplex 1: full-duplex 0 --- p, ro * link port link status 0: link off 1: link on 7.2.2 per port basic control register 1 (111h, 131h, 151h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 11h 111h, 131h, 151h bit rom type default description 15 --- ro 0b reserved write as 0b, ignore when read 14 80h.[14] 90h.[14] a0h.[14] pse,rw 0b unplug_cls unplug clear address enable automatically clear address record in address table after cable is unplugged 0: disable, retaining address record 1: enable, clearing address record 13 80h.[13] 90h.[13] a0h.[13] pse,rw 0b age_dis address table aging 0: age function is enabled 1: age function is disabled 12 80h.[12] 90h.[12] a0h.[12] pse,rw 0b adr_dis address learning disabled 0: address learning function is enabled 1: address learning function is disabled DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 29 DM8603-12-ds-p01 november 8, 2010 11 80h.[11] 90h.[11] a0h.[11] pse,rw 0b dis_pause maximum pause packet from link partner 0: always care pause packet from link partner 1: pause packet by passed after 7 continued pause packet from link partner 10 --- ro 0b reserved write as 0b, ignore when read 9 80h.[9] 90h.[9] a0h.[9] pse,rw 0b holbp_en head-of-line blocking prevent control 0: disable 1: enable 8 80h.[8] 90h.[8] a0h.[8] pse,rw 0b loopback loop-back mode the transmitted packet will be forward to this port itself 0: look-back is disabled 1: look-back is enabled 7 80h.[7] 90h.[7] a0h.[7] pse,rw 0b pause_con send pause continuously if buffer congestion occur on full duplex, switch will send pause frames: 0: up to 8-times 1: continuously until alleviation 6 80h.[6] 90h.[6] a0h.[6] pse,rw 0b parti_en partition detection enable 0: disable 1: enable 5 80h.[5] 90h.[5] a0h.[5] pse,rw 0b fcbp_dis backpressure flow-control in half duplex disable 0: backpressure is enabled 1: backpressure is disabled 4 80h.[4] 90h.[4] a0h.[4] pse,rw 0b fc3x_dis ieee 802.3x flow control in full duplex mode 0: 802.3x flow-control is enabled 1: 802.3x flow-control is disabled 3:2 80h.[3:2] 90h.[3:2] a0h.[3:2] pse,rw 00b max_pktlen[1:0] max accept packet length by rx from this port 00: 1536-bytes 01: 1552-bytes 10: 1800-bytes 11: 2032-bytes 1 80h.[1] 90h.[1] a0h.[1] pse,rw 0b rx_dis packet receive disable 0: receive ability is enabled 1: receive ability is disabled 0 80h.[0] 90h.[0] a0h.[0] pse,rw 0b tx_dis packet transmit disable 0: transmit ability is enabled 1: transmit ability is disabled DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 30 DM8603-12-ds-p01 november 8, 2010 7.2.3 per port basic control register 2 (112h, 132h, 152h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 12h 112h, 132h, 152h bit rom type default description 15 81h.[15] 91h.[15] a1h.[15] pse,rw 0b no_dis_rx not discard rx packets when ingress bandwidth control when received packets bandwidth reach ingress bandwidth threshold, the packets over the threshold are not discarded but with flow control. 14 81h.[14] 91h.[14] a1h.[14] pse,rw 0b bandwidth bandwidth control mode 0: separate mode. bandwidth control with ingress and egress is separated, the threshold defined in reg 08/09/0ah.15h.[15:8] 1: combined mode. bandwidth control with ingress or egress is combined, the threshold defined in reg 08/09/0ah.15h.[3:0] 13 81h.[13] 91h.[13] a1h.[13] pse,rw 0b storm_uup broadcast storm enable for unlearned unicast packets 0: disable 1: enable 12 81h.[12] 91h.[12] a1h.[12] pse,rw 0b storm_mp broadcast storm filtering for multicast packets treat multicast packet as source of storm 0: disable 1: enable 11 81h.[11] 91h.[11] a1h.[11] pse,rw 0b mirr_dbp don't mirror broadcast/multicast packets if mirror function is enabled 0: broadcast/multicast would be mirrored 1: broadcast/multicast would not be mirrored 10:9 --- ro 00b reserved write as 00b, ignore when read 8 81h.[8] 91h.[8] a1h.[8] pse,rw 0b fir_uudmac filter packets with unlearned unicast dmac 0: disable 1: enable 7 81h.[7] 91h.[7] a1h.[7] pse,rw 0b fir_umdmac filter packets with unlearned multicast dmac 0: disable 1: enable 6 81h.[6] 91h.[6] a1h.[6] pse,rw 0b fir_bdmac filter packets with broadcast dmac 0: disable 1: enable 5 81h.[5] 91h.[5] a1h.[5] pse,rw 0b fir_mdmac filter packets with multicast dmac 0: disable 1: enable 4 81h.[4] 91h.[4] a1h.[4] pse,rw 0b fir_msmac filter packets with multicast smac 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 31 DM8603-12-ds-p01 november 8, 2010 3 --- ro 0b reserved write as 0b, ignore when read 2 81h.[2] 91h.[2] a1h.[2] pse,rw 0b mirr_tx tx packet is mirrored. the received packets are also forward to sniffer port. 0: don?t mirror 1: all transmitted packets is mirrored 1 --- ro 0b reserved write as 0b, ignore when read 0 81h.[0] 91h.[0] a1h.[0] pse,rw 0b mirr_rx rx packet is mirrored. the received packets are also forward to sniffer port. 0: don?t mirror 1: all received packets is mirrored 7.2.4 per port block control register 1 (113h, 133h, 153h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 13h 113h, 133h, 153h bit rom type default description 15:11 --- ro 0h reserved write as 0h, ignore when read 10:8 82h.[10:8] 92h.[10:8] a2h.[10:8] pse,rw 000b blk_mp[2:0] block packet with multicast dmac [10]: block such packet forward to port 2 [09]: block such packet forward to port 1 [08]: block such packet forward to port 0 0: disable 1: enable 7:3 --- ro 0h reserved write as 0h, ignore when read 2:0 82h.[2:0] 92h.[2:0] a2h.[2:0] pse,rw 000b blk_bp[2:0] block packet with broadcast dmac [02]: block such packet forward to port 2 [01]: block such packet forward to port 1 [00]: block such packet forward to port 0 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 32 DM8603-12-ds-p01 november 8, 2010 7.2.5 per port block control register 2 (114h, 134h, 154h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 14h 114h, 134h, 154h bit rom type default description 15:11 --- ro 0h reserved write as 0h, ignore when read 10:8 83h.[10:8] 93h.[10:8] a3h.[10:8] pse,rw 000b blk_ukp[2:0] block packet with unlearned unicast dmac [10]: block such packet forward to port 2 [09]: block such packet forward to port 1 [08]: block such pack et forward to port 0 0: disable 1: enable 7:3 --- ro 0h reserved write as 0h, ignore when read 2:0 83h.[2:0] 93h.[2:0] a3h.[2:0] pse,rw 000b blk_up[2:0] block packet with unicast dmac the received unicast packets are not forward to the assigned ports. [02]: block such packet forward to port 2 [01]: block such packet forward to port 1 [00]: block such pack et forward to port 0 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 33 DM8603-12-ds-p01 november 8, 2010 7.2.6 per port bandwidth control register (115h, 135h, 155h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 15h 115h, 135h, 155h bit rom type default description 15:12 84h.[15:12] 94h.[15:12] a4h.[15:12] pse,rw 0000b ingr ess[3:0] ingress rate control (separated mode) these bits define the bandwidth threshold that received packets over the threshold are discarded. 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps 11:8 84h.[11:8] 94h.[11:8] a4h.[11:8] pse,rw 0000b egress[3:0] egress rate control these bits define the bandwidth threshold that transmitted packets over the threshold are discarded. 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 34 DM8603-12-ds-p01 november 8, 2010 7:4 84h.[7:4] 94h.[7:4] a4h.[7:4] pse,rw 0000b bsth[3:0] broadcast storm threshold these bits define the bandwidth threshold that received broadcast packets over the threshold are discarded 0000: no broadcast storm control 0001: 8k packets/sec 0010: 16k packets/sec 0011: 64k packets/sec 0100: 5% 0101: 10% 0110: 20% 0111: 30% 1000: 40% 1001: 50% 1010: 60% 1011: 70% 1100: 80% 1101: 90% 111x: no broadcast storm control 3:0 84h.[3:0] 94h.[3:0] a4h.[3:0] pse,rw 0000b bw_ctrl[3:0] ingress and egress rate control (combined mode) received and transmitted bandwidth control these bits define the bandwidth threshold that transmitted or received packets over the threshold are discarded 0000: none 0001: 64kbps 0010: 128kbps 0011: 256kbps 0100: 512kbps 0101: 1mbps 0110: 2mbps 0111: 4mbps 1000: 8mbps 1001: 16mbps 1010: 32mbps 1011: 48mbps 1100: 64mbps 1101: 72mbps 1110: 80mbps 1111: 88mbps DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 35 DM8603-12-ds-p01 november 8, 2010 7.2.7 per port vlan tag register (116h, 136h, 156h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 16h 116h, 136h, 156h bit rom type default description 15:13 85h.[15:13] 95h.[15:13] a5h.[15:13] pse,rw 000b ppri[2:0] port vlan priority 12 85h.[12] 95h.[12] a5h.[12] pse,rw 0b pcfi port vlan cfi 11:0 85h.[11:0] 95h.[11:0] a5h.[11:0] pse,rw 001h pvid[11:0] port vlan identification 7.2.8 per port priority & vlan control register (117h, 137h, 157h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 17h 117h, 137h, 157h bit rom type default description 15 --- ro 0b reserved write as 0b, ignore when read 14 86h.[14] 96h.[14] a6h.[14] pse,rw 0b tag_out output packet tagging enable the transmitted packets are containing vlan tagged field 0: disable 1: enable 13 86h.[13] 96h.[13] a6h.[13] pse,rw 0b fir_viport enable to filter packet with incoming port is non-member in vlan 0: disable 1: enable 12 86h.[12] 96h.[12] a6h.[12] pse,rw 0b notag_in input force no tag assume all received frame are untagged 0: disable 1: enable 11:10 --- ro 00b reserved write as 00b, ignore when read 9:8 86h.[9:8] 96h.[9:8] a6h.[9:8] pse,rw 00b vlan_iac[1:0] vlan ingress admit control 00: accept all frames 01: accept vlan-tagged frames only untagged or priority tagged(vid=0) frames will be dropped 10: accept untagged frames only 11: accept frame's vid equal to ingress pvid 7 --- ro 0b reserved write as 0b, ignore when read DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 36 DM8603-12-ds-p01 november 8, 2010 6 86h.[6] 96h.[6] a6h.[6] pse,rw 0b pri_dis priority queue disable only one transmit queue is supported in this port 0: priority queue is enabled 1: priority queue is disabled 5 86h.[5] 96h.[5] a6h.[5] pse,rw 0b wrr_en priority scheduling algorithm 0: strict priority queuing(spq) 1: weighted round robin(wrr) 4 86h.[4] 96h.[4] a6h.[4] pse,rw 0b tos_pri priority classification ip tos over vlan if a ip packet with vlan tag, the priority of this packet is decode from tos field. 0: priority classification base on vlan 1: priority classification base on ip tos 3 86h.[3] 96h.[3] a6h.[3] pse,rw 0b tos_off ip tos priority classification disable 0: classification is enabled 1: classification is disabled 2 86h.[2] 96h.[2] a6h.[2] pse,rw 0b pri_off vlan priority classification disable 0: classification is enabled 1: classification is disabled 1:0 86h.[1:0] 96h.[1:0] a6h.[1:0] pse,rw 00b p_pri[1:0] port-based priority queue number 00: queue 0 01: queue 1 10: queue 2 11: queue 3 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 37 DM8603-12-ds-p01 november 8, 2010 7.2.9 per port advanced control register (119h, 139h, 159h) phy_adr reg_adr abs_adr 08h, 09h, 0ah 19h 119h, 139h, 159h bit rom type default description 15:9 --- ro 0h reserved write as 0h, ignore when read 8 88h.[8] 98h.[8] a8h.[8] pse,rw 0b fast_l eave igmp snooping fast leave enable 0: disable 1: enable 7:2 --- ro 0h reserved write as 0h, ignore when read 1:0 --- ps,rw 00b stps0[1:0] stp/rstp port state. there are 4 port states for supporting stp, and 3 port states for supporting rstp. 00: forwarding state, the port transmits and receives packets normally & learning is enabled. 01: disabled state/discarding, the port will only forward the packets that are to and from up port (span packets) & learning is disabled. 10: learning state, the port will on ly forward the packets that are to and from up port (span packets) & leaning is enabled. 11: blocking/listening state, the port will only forward the packets that are to and from up port (span packets) & learning is disabled. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 38 DM8603-12-ds-p01 november 8, 2010 7.3 global switch register 7.3.1 switch status register (210h) phy_adr reg_adr abs_adr 10h 10h 210h bit rom type default description 15:2 --- ro 0h reserved write as 0h, ignore when read 1 --- ps, ro * bist_1 top-memory bist status 0: pass 1: fail 0 --- ps, ro * bist_0 packet-memory bist status 0: pass 1: fail 7.3.2 switch reset register (211h) phy_adr reg_adr abs_adr 10h 11h 211h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2 --- p, rw 0b pd_anlg power down all analog phy 1 --- p, rw 0b rst_anlg analog phy core reset auto clear after 10us 0 --- p, rw 0b rst_sw switch core reset auto clear after 10us DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 39 DM8603-12-ds-p01 november 8, 2010 7.3.3 switch control register (212h) phy_adr reg_adr abs_adr 10h 12h 212h bit rom type default description 15:6 --- ro 0h reserved write as 0h, ignore when read 5 12h.[5] pse,rw 0b fdx_flow flow control option when set in full duplex mode, if link partner?s flow control capability is disabled, the flow control of DM8603 corresponding port is also disabled. when this is ?0?, the flow control is controlled by reg 08~0ah.11h.[4]. 4:3 --- ro 00b reserved write as 00b, ignore when read 2 12h.[2] pse,rw 0b dis_crcc crc checking disable 0: crc checking is enabled 1: crc checking is disabled 1:0 --- ro 00b reserved write as 00b, ignore when read 7.3.4 mirror control register (213h) phy_adr reg_adr abs_adr 10h 13h 213h bit rom type default description 15:11 --- ro 0h reserved write as 0h, ignore when read 10 13h.[10] pse, rw 0b mirr_pair mirror rx/tx pair mode enable 0: disable (default) 1: enable 9:8 --- ro 00b reserved write as 00b, ignore when read 7 13h.[7] pse, rw 0b stag_txe special tag transmit enable 0: doesn't insert the special tag for outgoing packets 1: identifies the special tag for outgoing packets 6 13h.[6] pse, rw 0b stag_rxe special tag receive enable 0: doesn't identify the special tag for incoming packets 1: identifies the special tag for incoming packets 5 --- 0b reserved write as 0b, ignore when read DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 40 DM8603-12-ds-p01 november 8, 2010 4:3 13h.[4:3] pse, rw 00b snf_port[1 :0] sniffer port number 00: sniffer port is port 0 01: sniffer port is port 1 10: sniffer port is port 2 11: reserved 2:0 --- ro 000b reserved write as 000b, ignore when read 7.3.5 special tag ether-type register (214h) phy_adr reg_adr abs_adr 10h 14h 214h bit rom type default description 15:0 14h pse,rw 8606h stag_et ype[15:0] special tag ether-type 7.3.6 global learning & aging control register (215h) phy_adr reg_adr abs_adr 10h 15h 215h bit rom type default description 15:6 --- ro 0h reserved write as 0h, ignore when read 5 15h.[5] pse,rw 0b lrn_pause learn pause frame 0: disable (default) 1: enable 4 15h.[4] pse,rw 0b lrn_vlan address learning consider vlan member 0: address learning despite vlan member (default) 1: address learning is disable, if incoming port doesn't exist in its member set. 3:2 --- ro 00b reserved write as 00b, ignore when read 1:0 15h.[1:0] pse,rw 00b age_time[1:0] aging time value 00: 512 sec 01: 256 sec 10: 128 sec 11: 64 sec DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 41 DM8603-12-ds-p01 november 8, 2010 7.3.7 vlan priority map register (217h) phy_adr reg_adr abs_adr 10h 17h 217h bit rom type default description 15:14 1ch.[15:14] pse,rw 11b vlan_pm7[1:0] vlan tag priority value = 07h 13:12 1ch.[13:12] pse,rw 11b vlan_pm6[1:0] vlan tag priority value = 06h 11:10 1ch.[11:10] pse,rw 10b vlan_pm5[1:0] vlan tag priority value = 05h 9:8 1ch.[9:8] pse,rw 10b vlan_pm4[1:0] vlan tag priority value = 04h 7:6 1ch.[7:6] pse,rw 01b vlan_pm3[1:0] vlan tag priority value = 03h 5:4 1ch.[5:4] pse,rw 01b vlan_pm2[1:0] vlan tag priority value = 02h 3:2 1ch.[3:2] pse,rw 00b vlan_pm1[1:0] vlan tag priority value = 01h 1:0 1ch.[1:0] pse,rw 00b vlan_pm0[1:0] vlan tag priority value = 00h 7.3.8 tos priority map register 1 (218h) phy_adr reg_adr abs_adr 10h 18h 218h bit rom type default description 15:14 1dh.[15:14] pse,rw 11b tos_pm07[1:0] tos value = 07h 13:12 1dh.[13:12] pse,rw 11b tos_pm06[1:0] tos value = 06h 11:10 1dh.[11:10] pse,rw 10b tos_pm05[1:0] tos value = 05h 9:8 1dh.[9:8] pse,rw 10b tos_pm04[1:0] tos value = 04h 7:6 1dh.[7:6] pse,rw 01b tos_pm03[1:0] tos value = 03h 5:4 1dh.[5:4] pse,rw 01b tos_pm02[1:0] tos value = 02h 3:2 1dh.[3:2] pse,rw 00b tos_pm01[1:0] tos value = 01h 1:0 1dh.[1:0] pse,rw 00b tos_pm00[1:0] tos value = 00h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 42 DM8603-12-ds-p01 november 8, 2010 7.3.9 tos priority map register 2 (219h) phy_adr reg_adr abs_adr 10h 19h 219h bit rom type default description 15:14 1eh.[15:14] pse,rw 00b tos_pm0f[1:0] tos value = 0fh 13:12 1eh.[13:12] pse,rw 00b tos_pm0e[1:0] tos value = 0eh 11:10 1eh.[11:10] pse,rw 00b tos_pm0d[1:0] tos value = 0dh 9:8 1eh.[9:8] pse,rw 00b tos_pm0c[1:0] tos value = 0ch 7:6 1eh.[7:6] pse,rw 00b tos_pm0b[1:0] tos value = 0bh 5:4 1eh.[5:4] pse,rw 00b tos_pm0a[1:0] tos value = 0ah 3:2 1eh.[3:2] pse,rw 00b tos_pm09[1:0] tos value = 09h 1:0 1eh.[1:0] pse,rw 00b tos_pm08[1:0] tos value = 08h 7.3.10 tos priority map register 3 (21ah) phy_adr reg_adr abs_adr 10h 1ah 21ah bit rom type default description 15:14 1fh.[15:14] pse,rw 01b tos_pm17[1:0] tos value = 17h 13:12 1fh.[13:12] pse,rw 01b tos_pm16[1:0] tos value = 16h 11:10 1fh.[11:10] pse,rw 01b tos_pm15[1:0] tos value = 15h 9:8 1fh.[9:8] pse,rw 01b tos_pm14[1:0] tos value = 14h 7:6 1fh.[7:6] pse,rw 01b tos_pm13[1:0] tos value = 13h 5:4 1fh.[5:4] pse,rw 01b tos_pm12[1:0] tos value = 12h 3:2 1fh.[3:2] pse,rw 01b tos_pm11[1:0] tos value = 11h 1:0 1fh.[1:0] pse,rw 01b tos_pm10[1:0] tos value = 10h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 43 DM8603-12-ds-p01 november 8, 2010 7.3.11 tos priority map register 4 (21bh) phy_adr reg_adr abs_adr 10h 1bh 21bh bit rom type default description 15:14 20h.[15:14] pse,rw 01b tos_pm1f[1:0] tos value = 1fh 13:12 20h.[13:12] pse,rw 01b tos_pm1e[1:0] tos value = 1eh 11:10 20h.[11:10] pse,rw 01b tos_pm1d[1:0] tos value = 1dh 9:8 20h.[9:8] pse,rw 01b tos_pm1c[1:0] tos value = 1ch 7:6 20h.[7:6] pse,rw 01b tos_pm1b[1:0] tos value = 1bh 5:4 20h.[5:4] pse,rw 01b tos_pm1a[1:0] tos value = 1ah 3:2 20h.[3:2] pse,rw 01b tos_pm19[1:0] tos value = 19h 1:0 20h. [1:0] pse,rw 01b tos_pm18[1:0] tos value = 18h 7.3.12 tos priority map register 5 (21ch) phy_adr reg_adr abs_adr 10h 1ch 21ch bit rom type default description 15:14 21h.[15:14] pse,rw 10b tos_pm27[1:0] tos value = 27h 13:12 21h.[13:12] pse,rw 10b tos_pm26[1:0] tos value = 26h 11:10 21h.[11:10] pse,rw 10b tos_pm25[1:0] tos value = 25h 9:8 21h.[9:8] pse,rw 10b tos_pm24[1:0] tos value = 24h 7:6 21h.[7:6] pse,rw 10b tos_pm23[1:0] tos value = 23h 5:4 21h.[5:4] pse,rw 10b tos_pm22[1:0] tos value = 22h 3:2 21h.[3:2] pse,rw 10b tos_pm21[1:0] tos value = 21h 1:0 21h.[1:0] pse,rw 10b tos_pm20[1:0] tos value = 20h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 44 DM8603-12-ds-p01 november 8, 2010 7.3.13 tos priority map register 6 (21dh) phy_adr reg_adr abs_adr 10h 1dh 21dh bit rom type default description 15:14 22h.[15:14] pse,rw 10b tos_pm2f[1:0] tos value = 2fh 13:12 22h.[13:12] pse,rw 10b tos_pm2e[1:0] tos value = 2eh 11:10 22h.[11:10] pse,rw 10b tos_pm2d[1:0] tos value = 2dh 9:8 22h.[9:8] pse,rw 10b tos_pm2c[1:0] tos value = 2ch 7:6 22h.[7:6] pse,rw 10b tos_pm2b[1:0] tos value = 2bh 5:4 22h.[5:4] pse,rw 10b tos_pm2a[1:0] tos value = 2ah 3:2 22h.[3:2] pse,rw 10b tos_pm29[1:0] tos value = 29h 1:0 22h.[1:0] pse,rw 10b tos_pm28[1:0] tos value = 28h 7.3.14 tos priority map register 7 (21eh) phy_adr reg_adr abs_adr 10h 1eh 21eh bit rom type default description 15:14 23h.[15:14] pse,rw 11b tos_pm37[1:0] tos value = 37h 13:12 23h.[13:12] pse,rw 11b tos_pm36[1:0] tos value = 36h 11:10 23h.[11:10] pse,rw 11b tos_pm35[1:0] tos value = 35h 9:8 23h.[9:8] pse,rw 11b tos_pm34[1:0] tos value = 34h 7:6 23h.[7:6] pse,rw 11b tos_pm33[1:0] tos value = 33h 5:4 23h.[5:4] pse,rw 11b tos_pm32[1:0] tos value = 32h 3:2 23h.[3:2] pse,rw 11b tos_pm31[1:0] tos value = 31h 1:0 23h.[1:0] pse,rw 11b tos_pm30[1:0] tos value = 30h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 45 DM8603-12-ds-p01 november 8, 2010 7.3.15 tos priority map register 8 (21fh) phy_adr reg_adr abs_adr 10h 1fh 21fh bit rom type default description 15:14 24h.[15:14] pse,rw 11b tos_pm3f[1:0] tos value = 3fh 13:12 24h.[13:12] pse,rw 11b tos_pm3e[1:0] tos value = 3eh 11:10 24h.[11:10] pse,rw 11b tos_pm3d[1:0] tos value = 3dh 9:8 24h.[9:8] pse,rw 11b tos_pm3c[1:0] tos value = 3ch 7:6 24h.[7:6] pse,rw 11b tos_pm3b[1:0] tos value = 3bh 5:4 24h.[5:4] pse,rw 11b tos_pm3a[1:0] tos value = 3ah 3:2 24h.[3:2] pse,rw 11b tos_pm39[1:0] tos value = 39h 1:0 24h.[1:0] pse,rw 11b tos_pm38[1:0] tos value = 38h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 46 DM8603-12-ds-p01 november 8, 2010 7.3.16 mib counter disable register (230h) phy_adr reg_adr abs_adr 11h 10h 230h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 16h.[2:0] pse,rw 000b mib_dis[2:0] per-port mib counter disable [2] port2 mib counter disabled [1] port1 mib counter disabled [0] port0 mib counter disabled 0: enable 1: disable 7.3.17 mib counter control register (231h) phy_adr reg_adr abs_adr 11h 11h 231h bit rom type default description 15 --- ps,ro 0b mib_ready counter data is ready 14:10 --- ro 0h reserved write as 0h, ignore when read 9:8 --- ps,rw 00b mib_cmd[1:0] command 00: clear after read 01: read only 10: clear specified port 11: clear all ports 7 --- ro 0b reserved write as 0b, ignore when read 6:5 --- ps,rw 00b mib_port[1:0] port index (0~2) 4:0 --- ps,rw 00000b mib_offset[4:0] counter offset (0~9) DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 47 DM8603-12-ds-p01 november 8, 2010 7.3.18 mib counter data register 1 (232h) phy_adr reg_adr abs_adr 11h 12h 232h bit rom type default description 15:0 --- ps,rw 0h mib_dl[15:0] counter data low byte (bit 15:00) 7.3.19 mib counter data register 2 (233h) phy_adr reg_adr abs_adr 11h 13h 233h bit rom type default description 15:0 --- ps,rw 0h mib_dh[15:0] counter data high byte(bit 31:16) mib counter (offset 00h): rx byte counter register mib counter (offset 01h): rx uni-cast packet counter register mib counter (offset 02h): rx multi-cast packet counter register mib counter (offset 03h): rx discard packet counter register mib counter (offset 04h): rx error packet counter register mib counter (offset 05h): tx byte counter register mib counter (offset 06h): tx uni-cast packet counter register mib counter (offset 07h): tx multi-cast packet counter register mib counter (offset 08h): tx discard packet counter register mib counter (offset 09h): tx error packet counter register DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 48 DM8603-12-ds-p01 november 8, 2010 7.3.20 vlan mode & rule control register (23eh) phy_adr reg_adr abs_adr 11h 1eh 23eh bit rom type default description 15 31h.[15] pse,rw 0b fir_vidfff drop packet with vid==0xfff enable drop incoming packet, if its vid is equal to 0xfff 0: disable 1: enable 14 31h.[14] pse,rw 0b fir_cfi drop packet with nonzero cfi enable drop incoming packet, if the cfi field is not equal to zero. 0: disable 1: enable 13:9 --- ro 0h reserved write as 0h, ignore when read 8 31h.[8] pse,rw 0b qinq_en vlan stacking enable (qinq) 0: disable 1: enable 7 31h.[7] pse,rw 0b tos6 full ip tos field for priority queue 0: check most significant 3-bit only of tos 1: check most significant 6-bit of tos 6 --- ro 0b reserved write as 0b, ignore when read 5 31h.[5] pse,rw 0b ucross unicast packet can across vlan boundary 0: unicast packet obeys vlan rule 1: unicast packet can across vlan boundary 4 31h.[4] pse,rw 0b vid fff replace vid = 0xfff when receive a vlan tagged packet and vid equals to ?0xfff?, the outgoing packet's vid will be replaced by pvid. 0: disable 1: enable 3 31h.[3] pse,rw 0b vid1 when receive a vlan tagged packet and vid equals to ?0x001?, the outgoing packet's vid will be replaced by pvid. 0: disable 1: enable 2 31h.[2] pse,rw 0b vid0 replace vid = 0x000 when receive a vlan tagged packet and vid equals to ?0x000?, the outgoing packet's vid will be replaced by pvid. 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 49 DM8603-12-ds-p01 november 8, 2010 1 31h.[1] pse,rw 0b vlan_rpri replace vlan priority replace the received packet's vlan priority by reg 08h/09h/0ah.16h.[15:13] 0: disable 1: enable 0 31h.[0] pse,rw 0b vlan mode selection 0: port-based vlan 1: tag-based vlan DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 50 DM8603-12-ds-p01 november 8, 2010 7.3.21 vlan table register 0 (270h) phy_adr reg_adr abs_adr 13h 10h 270h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 43h.[2:0] pse,rw 111b vtab_vmb0[2:0] vlan entry 0 vlan member 7.3.22 vlan table register 1 (271h) phy_adr reg_adr abs_adr 13h 11h 271h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 44h.[2:0] pse,rw 111b vtab_vmb1[2:0] vlan entry 1 vlan member 7.3.23 vlan table register 2 (272h) phy_adr reg_adr abs_adr 13h 12h 272h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 45h.[2:0] pse,rw 111b vtab_vmb2[2:0] vlan entry 2 vlan member 7.3.24 vlan table register 3 (273h) phy_adr reg_adr abs_adr 13h 13h 273h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 46h.[2:0] pse,rw 111b vtab_vmb3[2:0] vlan entry 3 vlan member DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 51 DM8603-12-ds-p01 november 8, 2010 7.3.25 vlan table register 4 (274h) phy_adr reg_adr abs_adr 13h 14h 274h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 47h.[2:0] pse,rw 111b vtab_vmb4[2:0] vlan entry 4 vlan member 7.3.26 vlan table register 5 (275h) phy_adr reg_adr abs_adr 13h 15h 275h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 48h.[2:0] pse,rw 111b vtab_vmb5[2:0] vlan entry 5 vlan member 7.3.27 vlan table register 6 (276h) phy_adr reg_adr abs_adr 13h 16h 276h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 49h.[2:0] pse,rw 111b vtab_vmb6[2:0] vlan entry 6 vlan member 7.3.28 vlan table register 7 (277h) phy_adr reg_adr abs_adr 13h 17h 277h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4ah.[2:0] pse,rw 111b vtab_vmb7[2:0] vlan entry 7 vlan member DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 52 DM8603-12-ds-p01 november 8, 2010 7.3.29 vlan table register 8 (278h) phy_adr reg_adr abs_adr 13h 18h 278h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4bh.[2:0] pse,rw 111b vtab_vmb8[2:0] vlan entry 8 vlan member 7.3.30 vlan table register 9 (279h) phy_adr reg_adr abs_adr 13h 19h 279h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4ch.[2:0] pse,rw 111b vtab_vmb9[2:0] vlan entry 9 vlan member 7.3.31 vlan table register 10 (27ah) phy_adr reg_adr abs_adr 13h 1ah 27ah bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4dh.[2:0] pse,rw 111b vtab_vmb10[2:0] vlan entry 10 vlan member 7.3.32 vlan table register 11 (27bh) phy_adr reg_adr abs_adr 13h 1bh 27bh bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4eh.[2:0] pse,rw 111b vtab_vmb11[2:0] vlan entry 11 vlan member DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 53 DM8603-12-ds-p01 november 8, 2010 7.3.33 vlan table register 12 (27ch) phy_adr reg_adr abs_adr 13h 1ch 27ch bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 4fh.[2:0] pse,rw 111b vtab_vmb12[2:0] vlan entry 12 vlan member 7.3.34 vlan table register 13 (27dh) phy_adr reg_adr abs_adr 13h 1ch 27dh bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 50h.[2:0] pse,rw 111b vtab_vmb13[2:0] vlan entry 13 vlan member 7.3.35 vlan table register 14 (27eh) phy_adr reg_adr abs_adr 13h 1eh 27eh bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 51h.[2:0] pse,rw 111b vtab_vmb14[2:0] vlan entry 14 vlan member 7.3.36 vlan table register 15 (27fh) phy_adr reg_adr abs_adr 13h 1fh 27fh bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 52h.[2:0] pse,rw 111b vtab_vmb15[2:0] vlan entry 15 vlan member DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 54 DM8603-12-ds-p01 november 8, 2010 7.3.37 stp control register (292h) phy_adr reg_adr abs_adr 14h 12h 292h bit rom type default description 15:1 --- ro 0h reserved write as 0h, ignore when read 0 --- ps,rw 0b stpen spanning tree protocol enable 0: disable 1: enable 7.3.38 snooping control register 1 (29bh) phy_adr reg_adr abs_adr 14h 1bh 29bh bit rom type default description 15:11 --- ro 0h reserved write as 0h, ignore when read 10:8 17h.[10:8] pse,rw 111b rpp[2:0] router port portmap bit0: port 0 bit1: port 1 bit2: port 2 7 17h. [8] pse,rw 0b ud_rp user-defined router port enable 0: router port is manipulated by hardware 1: router port is user-defined 6 --- ro 0b reserved write as 0b, ignore when read 5:4 17h. [5:4] pse,rw 00b mcp_h[1:0] multicast control packet handle 00: forward membership reports to router port. general query to all port. 01: mirror to cpu (forward to cpu also) 10: trap to cpu (forward to cpu only) 11: flood 3:2 17h. [3:2] pse,rw 00b umd_ctrl[1:0] unregistered multicast data packet handle 00: as normal multicast packets 01: dropped 10: trap to cpu 11: flood except cpu 1 17h. [1] pse,rw 0b mlds_en mld snooping enable 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 55 DM8603-12-ds-p01 november 8, 2010 0 17h. [0] pse,rw 0b higs_en hardware igmp snooping enable 0: disable 1: enable 7.3.39 snooping control register 2 (29ch) phy_adr reg_adr abs_adr 14h 1ch 29ch bit rom type default description 15:13 --- ro 000b reserved write as 000b, ignore when read 12 18h.[12] pse,rw 0b igs_todis igmp snooping timeout scheme disable 0: timeout is enabled 1: timeout is disabled 11:10 18h. [11:10] pse,rw 10b rp_tv[1:0] router port timeout value selection 00: 1 times of query interval 01: 2 times of query interval 10: 3 times of query interval (default) 11: 4 times of query interval 9:8 18h. [9:8] pse,rw 01b igs_rv[1:0] robustness variable 00: 1 times 01: 2 times (default) 10: 3 times 11: 4 times 7:0 18h. [7:0] pse,rw 7dh igs_qi[7:0] query interval default = 8?h7d (sec) DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 56 DM8603-12-ds-p01 november 8, 2010 7.3.40 address table control & status register (2b0h) phy_adr reg_adr abs_adr 15h 10h 2b0h bit rom type default description 15 --- ps,ro 0b atb_s address table access is busy 0: available (access process is completed) 1: busy (access process is operating) 14:13 --- ps,rw 00b atb_cr[1:0] address table command result 00: command ok, entry doesn't exist a. create an new entry (write command) b. do noting (delete command) c. not found (search command) d. entry is invalid (read command) 01: command ok, entry is exist a. overwrite entry (write command) b. delete entry (delete command) c. entry found (search command) d. entry is valid (read command) 1x: command error 12:5 --- ro 0h reserved write as 0h, ignore when read 4:2 --- ps,rw 000b atb_cmd[2:0] command 000: read a entry with sequence number of address table 001: write a entry with mac address 010: delete a entry with mac address 011: search a entry with mac address 1:0 --- ps,rw 00b atb_idx[1:0] address table index 00: unicast address table 01: multicast address table 10: igmp table 11: reserved DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 57 DM8603-12-ds-p01 november 8, 2010 7.3.41 address table data register 1 (2b1h) phy_adr reg_adr abs_adr 15h 11h 2b1h bit rom type default description 15:3 --- ro 0h reserved write as 0h, ignore when read 2:0 --- ps,rw 000b atb_port[2:0] address table port number or port map 7.3.42 address table data register 2 (2b2h) phy_adr reg_adr abs_adr 15h 12h 2b2h bit rom type default description 15:0 --- ps,rw 0h atb_dw1[15:0] address table data word 1 7.3.43 address table data register 3 (2b3h) phy_adr reg_adr abs_adr 15h 13h 2b3h bit rom type default description 15:0 --- ps,rw 0h atb_dw2[15:0] address table data word 2 7.3.44 address table data register 4 (2b4h) phy_adr reg_adr abs_adr 15h 14h 2b4h bit rom type default description 15:0 --- ps,rw 0h atb_dw3[15:0] address table data word 3 7.3.45 address table data 4 register (2b5h) phy_adr reg_adr abs_adr 15h 15h 2b5h bit rom type default description 15:0 --- ps,rw 0h atb_dw4[15:0] address table data word 4 7.3.46 vendor id register (310h) DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 58 DM8603-12-ds-p01 november 8, 2010 phy_adr reg_adr abs_adr 18h 10h 310h bit rom type default description 15:0 04h.[15:0] pe,ro 0a46h vid[15:0] vendor id 7.3.47 product id register (311h) phy_adr reg_adr abs_adr 18h 11h 311h bit rom type default description 15:0 05h.[15:0] pe,ro 8603h pid[15:0] product id DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 59 DM8603-12-ds-p01 november 8, 2010 7.3.48 port 2 mac control register (315h) phy_adr reg_adr abs_adr 18h 15h 315h bit rom type default description 15:10 --- ro 0h reserved write as 0h, ignore when read 9:8 0dh.[9:8] pe,rw 01b p2_curr[9:8] port 2 txd/txe current driving/sinking capability 00: 2ma 01: 4ma (default) 10: 6ma 11: 8ma 7:4 --- ro 0h reserved write as 0h, ignore when read 3 0dh. [3] pset,rw * p2_mode port2 status in auto-polling mode for mii/revmii/rmii 0: auto-polling mode 1: force mode * the default value comes from the strap pin (p2_txe) and eeprom loading sequentially: p2_txe 0: pull-low 1: pull-high 2 0dh. [2] pse,rw 0b p2_link when port2 in force mode for mii/revmii/rmii 0: link on 1: link off 1 0dh. [1] pse,rw 0b p2_dpx when port2 in force mode for mii/revmii/rmii 0: full-duplex mode 1: half-duplex mode 0 0dh. [0] pset,rw * p2_speed when port2 in force mode for mii/revmii/rmii 0: 100m mode 1: 10m mode * the default value comes from the strap pins (p2_txe, eeck) and eeprom loading sequentially: p2_txe eeck 0: pull-low don't care 0: pull-high pull-high 1: pull-high pull-low DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 60 DM8603-12-ds-p01 november 8, 2010 7.3.49 eeprom control & address register (31ah) phy_adr reg_adr abs_adr 18h 1ah 31ah bit rom type default description 15:8 --- ps,rw 0h eroa[7:0] eeprom word address 7 --- ro 0b reserved write as 0b, ignore when read 6 --- p,rw 1b eetype eeprom type 0: 93c46 1: 93c56/66(default) 5 --- ps,rw 0b reep reload eeprom. user needs to clear it up after the operation completes 4 --- ps,rw 0b wep write eeprom enable 0: eeprom write operation is disabled 1: eeprom write operation is enabled 3 --- ps,rw 0b epos external phy operation select 0: select eeprom 1: select external phy 2 --- ps,rw 0b erprr eeprom read command user needs to clear it up after the operation completes 1 --- ps,rw 0b erprw eeprom write command user needs to clear it up after the operation completes 0 --- ps,ro 0b erre eeprom or phy access status 0: idle 1: eeprom or phy access is in progress 7.3.50 eeprom data register (31bh) phy_adr reg_adr abs_adr 18h 1bh 31bh bit rom type default description 15:0 --- ps,rw 0h ee_data[15:0] eeprom 16bit data DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 61 DM8603-12-ds-p01 november 8, 2010 7.3.51 strap pin control & status register (31ch) phy_adr reg_adr abs_adr 18h 1ch 31ch bit rom type default description 15 --- pt,ro * h_test3 hard-strap test3 * the default value depend on the pin, test3 14 --- pt,ro * h_test2 hard-strap test2 * the default value depend on the pin, test2 13 --- pt,ro * h_test1 hard-strap test1 * the default value depend on the pin, test1 12 --- rw --- reserved write as 0b, ignore when read 11 --- ro --- reserved write as 0b, ignore when read 10 --- pt,ro * h_eecs hard-strap eecs * the default value depend on the strap pin, eecs 9 --- pt,ro * h_eeck hard-strap eeck * the default value depend on the strap pin, eeck 8:6 --- ro --- reserved write as 000b, ignore when read 5 --- pt,rw * hs_txer2 hard-strap/soft-strap p2_txer * the default value depend on the strap pin, p2_txer 4 --- pt,rw * hs_txe2 hard-strap/soft-strap p2_txe * the default value depend on the strap pin, p2_txe 3 --- pt,rw * hs_txd23 hard-strap/soft-strap p2_txd3 * the default value depend on the strap pin, p2_txd3 2 --- pt,rw * hs_txd22 hard-strap/soft-strap p2_txd2 * the default value depend on the strap pin, p2_txd2 1:0 --- rw --- reserved write as 0b, ignore when read note 1. the default value of hard-strap in reg 18h.1ch depends on each pins' strap setting when power-on reset, refer to the section 5. 8 strap pins table for more detail. 2. the hard-strap's setting can be overridden via soft- strap (reg 18h.1ch.[5:0]). the updated setting will be applied until software reset is asserted (write reg 10h.11h.[0] to 1). DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 62 DM8603-12-ds-p01 november 8, 2010 7.3.52 smi bus error check register (339h) phy_adr reg_adr abs_adr 19h 19h 339h bit rom type default description 15:9 -- ro 0h reserved write as 0h, ignore when read 8 --- ps,ro 0b smi_err smi bus error status(read only) 0: checksum check correct 1: checksum check error 7:0 --- ps,rw 0h smi_csum[7:0] smi bus command checksum calculated checksum value by hw 7.3.53 smi bus control register (33ah) phy_adr reg_adr abs_adr 19h 1ah 33ah bit rom type default description 15:1 --- ro 0h reserved write as 0h, ignore when read 0 --- p,rw 0b smi_ece smi bus error check enable 0: disable 1: enable DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 63 DM8603-12-ds-p01 november 8, 2010 7.3.54 phy control register (33eh) phy_adr reg_adr abs_adr 19h 1eh 33eh bit rom type default description 15 07h.[15] pse,rw 0b mdix_dis_p0 port0 auto-mdix control 0: auto_mdix enable 1: auto_mdix disable 14 07h. [14] pse,rw 0b mdix_dis_p1 port1 auto-mdix control 0: auto_mdix enable 1: auto_mdix disable 13:9 --- ro 0h reserved write as 0h, ignore when read 8 07h. [8] pset,rw 0b phy_lfp_en phy lfp control 0: phy lfp disable 1: phy lfp enable 7:4 --- ro 0h reserved write as 0h, ignore when read 3:0 --- ps,rw 3h i_tune_tx[3:0] tx operation current to tune the tx operation current note: there are two method to control auto-mdix ability on each port, switch reg 19h.1eh.[15:14] and per-port's phy reg 02h/03h.14h.[4]. for instance, we can control port 0's auto-mdix ability by: auto-mdix switch reg 19h.1eh.[15] port 0's phy reg 02h.14h.[4] enable 0 0 disable 1 don't care disable don't care 1 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 64 DM8603-12-ds-p01 november 8, 2010 8. eeprom format name word description signature 00h when this word is 1049h, the eeprom data is valid and can be loaded to DM8603. reserved 01h~02h reserved set to ?0000h? in application load control 0 03h bit [01:00] = load enable of word 04h & 05h 01b: enable, 00b/10b/11b: disable bit [03:02] = reserved set to ?00b? or ?11b? in application bit [05:04] = load enable of word 07h 01b: enable, 00b/10b/11b: disable bit [07:06] = load enable of word 09h & 0ah 01b: enable, 00b/10b/11b: disable bit [09:08] = load enable of word 0dh 01b: enable, 00b/10b/11b: disable bit [11:10] = reserved set to ?00b? or ?11b? in application bit [13:12] = reserved set to ?00b? or ?11b? in application bit [15:14] = reserved set to ?00b? or ?11b? in application vendor id 04h 2 byte vendor id (default: 0a46h) if bit [1:0] of word 03h is ?01b?, bit [15:0] will be loaded to reg 18h.10h product id 05h 2 byte product id (default: 8603h) if bit [1:0] of word 03h is ?01b?, bit [15:0] will be loaded to reg 18h.11h reserved 06h reserved set to ?0000h? in application phy control 07h phy auto-mdix control if bit [5:4] of word 03h is ?01b?, bit [07:00] = reserved bit [08] = phy lfp control 1: on, 0: off bit [13:09] = reserved bit [14] = port 1 auto-mdix control 1: on, 0: off(default on) bit [15] = port 0 auto-mdix control 1: on 0: off(default on) reserved 08h reserved set to ?0000h? in application phy vendor id 09h 2 byte phy id1 if bit [7:6] of word 03h is ?01b?, bit[15:0] will be loaded to phy vendor id. phy device id 0ah 2 byte phy id2 if bit [7:6] of word 03h is ?01b?, bit[15:0] will be loaded to phy device id. reserved 0bh~0ch reserved set to ?0000h? in application port 2 mac control 0dh port 2 mac control DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 65 DM8603-12-ds-p01 november 8, 2010 if bit [9:8] of word 03h is ?01b?, bit [15:0] will be loaded to reg 18h.15h load control 1 0eh bit [01:00] = load enable of word 12h ~ 16h 01b: enable, 00b/10b/11b: disable bit [03:02] = load enable of word 17h &18h 01b: enable, 00b/10b/11b: disable bit [05:04] = load enable of word 1ch ~ 24h 01b: enable, 00b/10b/11b: disable bit [07:06] = reserved set to ?00b? or ?11b? in application bit [09:08] = load enable of word 31h ~ 52h 01b: enable, 00b/10b/11b: disable bit [11:10] = reserved set to ?00b? or ?11b? in application bit [13:12] = reserved set to ?00b? or ?11b? in application bit [15:14] = reserved set to ?00b? or ?11b? in application load control 2 0fh bit [01:00] = load enable of word 80h ~ 8ah 01b: enable, 00b/10b/11b: disable bit [03:02] = load enable of word 90h ~ 9ah 01b: enable, 00b/10b/11b: disable bit [05:04] = load enable of word a0h ~ aah 01b: enable, 00b/10b/11b: disable bit [07:06] = reserved set to ?00b? or ?11b? in application bit [09:08] = reserved set to ?00b? or ?11b? in application bit [11:10] = reserved set to ?00b? or ?11b? in application bit [13:12] = reserved set to ?00b? or ?11b in application bit [15:14] = reserved set to ?00b? or ?11b? in application reserved 10h~11h reserved set to ?0000h? in application switch control 12h if bit [01:00] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.12h mirror control 13h if bit [01:00] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.13h special tag ether-type 14h if bit [01:00] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.14h global learning & aging control 15h if bit [01:00] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.15h mib counter disable 16h if bit [01:00] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 11h.10h snoop ctrl 0 17h if bit [03:02] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 14h.1bh snoop ctrl 1 18h if bit [03:02] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 14h.1ch reserved 19h~1bh reserved set to ?0000h? in application vlan priority map register 1ch if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.17h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 66 DM8603-12-ds-p01 november 8, 2010 tos priority map 0 1dh if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.18h tos priority map 1 1eh if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.19h tos priority map 2 1fh if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1ah tos priority map 3 20h if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1bh tos priority map 4 21h if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1ch tos priority map 5 22h if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1dh tos priority map 6 23h if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1eh tos priority map 7 24h if bit [05:04] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 10h.1fh reserved 25h~30h reserved set to ?0000h? in application vlan mode & rule control 31h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 11h.1eh reserved 32h~42h reserved set to ?0000h? in application vlan table - member_0h 43h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.10h vlan table - member_1h 44h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.11h vlan table - member_2h 45h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.12h vlan table - member_3h 46h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.13h vlan table - member_4h 47h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.14h vlan table - member_5h 48h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.15h vlan table - member_6h 49h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.16h vlan table - member_7h 4ah if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.17h vlan table - member_8h 4bh if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.18h vlan table - member_9h 4ch if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.19h vlan table - member_ah 4dh if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.1ah vlan table - member_bh 4eh if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.1bh vlan table - member_ch 4fh if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.1ch vlan table - member_dh 50h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.1dh vlan table - member_eh 51h if bit [09:08] of word 0eh is ?01b?, bit [15:00] will be loaded to reg 13h.1eh vlan table - 52h if bit [09:08] of word 0eh is ?01b?, DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 67 DM8603-12-ds-p01 november 8, 2010 member_fh bit [15:00] will be loaded to reg 13h.1fh reserved 53h~7fh reserved set to ?0000h? in application p0 basic control 0 80h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.11h p0 basic control 1 81h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.12h p0 block control 0 82h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.13h p0 block control 1 83h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.14h p0 bandwidth control 84h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.15h p0 vlan tag information 85h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.16h p0 priority & vlan control 86h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.17h reserved 87h reserved set to ?0000h? in application p0 advanced control 88h if bit [01:00] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 08h.19h reserved 89h~8ah reserved set to ?0000h? in application reserved 8bh~8fh reserved set to ?0000h? in application p1 basic control 0 90h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.11h p1 basic control 1 91h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.12h p1 block control 0 92h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.13h p1 block control 1 93h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.14h p1 bandwidth control 94h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.15h p1 vlan tag information 95h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.16h p1 priority & vlan control 96h if bit [03:02] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 09h.17h reserved 97h reserved set to ?0000h? in application p1 advanced control 98h if bit [03:02] of word 0fhis ?01b?, bit [15:00] will be loaded to reg 09h.19h reserved 99h~9ah reserved set to ?0000h? in application reserved 9bh~9fh reserved set to ?0000h? in application p2 basic control 0 a0h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.11h p2 basic control 1 a1h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.12h p2 block control 0 a2h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.13h DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 68 DM8603-12-ds-p01 november 8, 2010 p2 block control 1 a3h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.14h p2 bandwidth control a4h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.15h p2 vlan tag information a5h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.16h p2 priority & vlan control a6h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.17h reserved a7h reserved set to ?0000h? in application p2 advanced control a8h if bit [05:04] of word 0fh is ?01b?, bit [15:00] will be loaded to reg 0ah.19h reserved a9h~aah reserved set to ?0000h? in application reserved abh~ffh reserved set to ?0000h? in application DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 69 DM8603-12-ds-p01 november 8, 2010 9. functional description 9.1 host serial management interface 9.1.1 host smi frame structure host smi - read frame structure host smi - write frame structure the host smi consists of two pins, one is smi_ mdc and another is smi_mdio. user can access DM8603?s eeprom, phy registers, mib counters and configurat ion registers through ho st smi. the format is following. the DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 70 DM8603-12-ds-p01 november 8, 2010 9.1.2 host smi bus error check function because smi bus tends to be interfered by noise on board-level. this function is used to check the command validity to suppress the mistaken command. in write procedure, the written value in register will be applied until the correct checksum is wr itten (error proofing) and user can read status for validation (error detecting). in read procedure, user can compare hard ware calculated checksum with software calculated one to validate the result. for example: z write procedure (1). set reg 19h.1ah.[0] = 1 to enable smi bus error check function (2). write data to DM8603's register (general write command) (3). cpu calculate checksum (csum[7: 0]) and write it to reg 19h.19h.[7:0] (4). check function status reg 19h.19h.[8] z read procedure (1). set reg 19h.1ah.[0] = 1 to enable smi bus error check function (2). read data from DM8603's register (general read command) (3). read hardware calculated checksum from reg 19h.19h.[7:0] and compare it with cpu calculated one (csum[7:0]) checksum calculate formula: csum[0] = d[0] ^ d[8] ^ r[0] ^ a[3] csum[1] = d[1] ^ d[9] ^ r[1] ^ a[4] csum[2] = d[2] ^ d[10] ^ r[2] ^ op[0] csum[3] = d[3] ^ d[11] ^ r[3] ^ op[1] csum[4] = d[4] ^ d[12] ^ r[4] csum[5] = d[5] ^ d[13] ^ a[0] csum[6] = d[6] ^ d[14] ^ a[1] csum[7] = d[7] ^ d[15] ^ a[2] note: d[15:0] = field of smi frame r[4:0] = DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 71 DM8603-12-ds-p01 november 8, 2010 9.2 switch functions 9.2.1 address learning the DM8603 has a self-learning mechanism for learni ng the mac addresses of incoming packets in real time. DM8603 stores mac addresses, port number and time stamp information in the hash-based address table. it can learn up to 1k unicast address entries. the switch engine updates address table with new entr y if incoming packet?s source address (sa) does not exist and incoming packet is valid (non-error and legal length). besides, DM8603 has an option to disable address learni ng for individual port. this feature can be set by reg 08h/09h/0ah.11h.[12]. 9.2.2 address aging the time stamp information of address table is us ed in the aging process. the switch engine updates time stamp whenever the corresponding sa receives. the switch engine would delete the entry if its time stamp is not updated for a period of time. the period can be programmed or disabled through reg 10h.15h.[1:0]. 9.2.3 packet forwarding the DM8603 forwards the incoming packet according to following decision: z if da is multicast/broadcast, the packet is forwar ded to all ports, except to the port on which the packet was received. z switch engine would look up address table based on da when incoming packets is unicast. if the da was not found in address table, the packet is treated as a mult icast packet and forward to other ports. if the da was found and its destination port number is different to source port number, the packet is forward to destination port. z switch engine also look up vlan, port monitor setting and other forwarding constraints for the forwarding decision, more detail will discuss in later sections. the DM8603 will filter incoming packets under following conditions: z error packets, including crc errors, alignment errors, illegal size errors. z pause packets. z if incoming packet is unicast and its destinatio n port number is equal to source port number. 9.2.4 inter-packet gap (ipg) ipg is the idle time between any two valid packets at t he same port. the typical number is 96 bits time. in other word, the value is 9.6u sec for 10mbps and 960n sec for 100mbps. 9.2.5 back-off algorithm the DM8603 implements the binary exponential back-off algorithm in half-duplex mode compliant to ieee standard 802.3. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 72 DM8603-12-ds-p01 november 8, 2010 9.2.6 late collision late collision is a type of collision. if a collision er ror occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 full duplex flow control the DM8603 supports ieee standard 8 02.3x flow control frames on both transmit and rece ive sides. on the receive side, the DM8603 will defer transmitting next normal frames, if it receives a pause frame from link partner. on the transmit side, the DM8603 issues pause frame with maximum pause time when internal resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. once resources are available, the DM8603 sends out a pause fr ame with zero pause time allows traffic to resume immediately. 9.2.8 half duplex flow control the DM8603 supports half-duplex backpressure. the inducement is the same as full duplex mode. when flow control is required, the DM8603 sends jam pattern and results in a collision. the flow control ability can be set in reg 08h/09h/0ah.11h.[5]. 9.2.9 partition mode the DM8603 provides a partition mode for each port, see reg 08h/09h/0ah.11h.[6]. the port enters partition mode when more than 64 consecutive collisions are occurred. in partition mode the port continuous to transmit but it will not receive. the port returned to normal operation mode when a good packet is seen on the wire. the detail description of partition mode represent following: (1). entering partition state a port will enter the partition state when ei ther of the following conditions occurs: z the port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet. z the port detects a single collision which occurs for more than 512 bit times. z transmit defer timer time out, which indicates the transmitting packet is deferred to long. (2). while in partition state: the port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the usual back-off algorithm. additional packets pending for transmission will be transmitted, while ignoring the internal collision i ndication. this frees up t he ports transmit buffers which would otherwise be filled up at the expense of other ports buffers. the assumption is that the partition is signifying a syst em failure situation (bad connecti on/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a buffer full condition. (3). exiting from partition state the port exits from partition state, following t he end of a successful packet transmission. a successful packet transmission is defined as no collisions were detected on the first 512 bits of the transmission. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 73 DM8603-12-ds-p01 november 8, 2010 9.2.10 broadcast storm filtering the DM8603 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. there are two types of broadcast st orm control, one is throttling broadca st packet only, the other includes multicast. this feature can be se t through reg 08h/09h/0ah.12h. the broadcast storm threshold can be programmed by eeprom or reg 08h/ 09h/0ah.15h, the default setting is no broadcast storm protecting. 9.2.11 bandwidth control the DM8603 supports two types of bandwidth control for each port. one is the ingress and egress bandwidth rate can be controlled separately, the other is combined together, this function can be set through reg 08h/09h/0ah.12h.[14]. the bandwidt h control is disabled by default. to separate and combined bandwidth control mode, the threshold rate is defined in reg 08h/09h/0ah.15h. the behavior of bandwidth control as below: (1). for the ingress contro l, if flow control function is enabled, pause or jam packet will be transmitted. the ingress packets will be dropped if flow control is disabled. (2). for the egress control, the egress port will not tran smit any packets. on t he other hand, the ingress bandwidth of source port will be throttled that prevent packets from forwarding. (3). in combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be throttled. 9.2.12 port monitoring support the DM8603 supports ?port monitoring? function on per port base, detail as below: (1). sniffer port and monitor port there is only one port can be selected as ?sniffer port? by reg 10h.13h, multiple ports can be set as ?receive monitor port? or ?transmit monitor port? in reg 08h/09h/0ah.12h. (2). receive monitor all packets received on the ?receive monitor port ? are send a copy to ?sniffer port?. for example, port 0 is set as ?receive monitor port? and port 2 is selected as a ?sniffer port?. if a packet is received form port 0 and predestined to port 1 afte r forwarding decision, the DM8603 will forward it to port 1 and port 2 in the end. (3). transmit monitor all packets transmitted on the ?trans mit monitor port? are send a copy to ?sniffer port?. for example, port 1 is set as ?transmit monitor port? and port 2 is selected as ?sniffer port?. if a packet is received from port 0 and predestined to port 1 after forwardi ng decision, the DM8603 will forward it to port 1 and port 2 in the end. (4). exception the DM8603 has an optional setting that broadcas t/multicast packets are not monitored (see reg 08h/09h/0ah.12h.[11]). it?s useful to avoid unnecessary bandwidth. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 74 DM8603-12-ds-p01 november 8, 2010 9.2.13 vlan support 9.2.13.1 port-based vlan the DM8603 supports port-based vlan as default, and up to 16 groups. each port has a default vid called pvid (port vid, see reg 08h/ 09h/0ah.16h). for vlan setting, the DM8603 used lsb 4-bytes of pvid as index and mapped to the vlan group mapping registers (reg 13h.10h~1fh) to decide the destination port(s). 9.2.13.2 802.1q-based vlan regarding ieee 802.1q standard, tag-based vlan uses an extra tag to identify the vlan membership of a frame across vlan-aware switch/router. a tagged frame is four bytes longer than an untagged frame and contains two bytes of tpid (tag protocol identifi er) and two bytes of tci (tag control information). the DM8603 also supports 16 802.1q-based vlan grou ps, as specified in reg 11h.1eh.[0]. it?s obvious that the tagged packets can be assigned to several diffe rent vlans which are determined according to the vid inside the vlan tag. therefor e, the operation is similar to port-based vlan. the DM8603 used lsb 4-bytes vid of received packet with vlan tag an d vlan group mapping register (reg 13h.10h~1fh) to configure the vlan partition. if the destination port of received packet is not same vlan group with received port, it will be discarded. dest. src. length/type data dest. src. tpid data tci length / type priority cfi vid standard frame tagged frame 0x8100 2 bytes 3 bits 1 bits 12 bits 9.2.13.3 tag/untag user can define each port as tag port or un-tag port by reg 08h/09h/0ah.17h .[14] in 802.1q-based vlan mode. the operation of tag and un-tag can explain as below conditions: (1). receive untagged packet and forward to un-tag port. received packet will forward to destination port without modification. (2). receive tagged packet and forward to un-tag port. the DM8603 will re move the tag from the packet and recalculate crc before sending it out. (3). receive untagged packet and forward to tag port. the DM8603 will insert the pvid tag when an untagged packet enters the port, and recalculate crc before delivering it. (4). receive tagged packet and forward to tag por t. received packet will fo rward to destination port without modification. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 75 DM8603-12-ds-p01 november 8, 2010 9.2.14 special tag the special tag function provided by the DM8603 is used to exchange control and status information between switch and cpu within frame. an extra 4-byte s tag is added into frame to carry different content according to direction of special t ag frame. received special tag (cpu ? switch) specifies the desired port mapping of packet sent by cpu and some configurati ons about frame handle rules. transmitted special tag (switch ? cpu) indicates the source port number of incoming frame. the following figure shows special tag frame format. in left 2 bytes of special tag field, there is an identifier called special tag ether-type that can use to recognize special tag frame. the value of this field can be set by reg 10h.14h. the detail information carried by received special tag is described as below. through received special tag, cpu can tell switch the handle rule per frame ov er the internal setting. this feature can be enable through reg 10h.13h.[6]. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 76 DM8603-12-ds-p01 november 8, 2010 received special tag(cpu ? switch) 4-byte format: byte 0/1: [15:0] special tag ether-type (default: 0x8086) byte 2: [7] reserved [6] st_pmap_en, st_pmap enable [5:3] reserved [2:0] st_pmap, force to assign forwarding port map byte 3: [7] reserved [6] st_cvlan, cross vlan 0: this frame obeys vlan boundary. 1: this frame can cross vlan boundary. [5] st_lrn_dis, disable learning 0: this frame will be learned 1: this frame will not be learned [4] st_pri_en, st_pri enable [3:2] st_pri, priority queue number (0~3) 00: queue 0 01: queue 1 10: queue 2 11: queue 3 [1:0] st_tag 00: unmodified 01: always tagged 10: always untagged 11: reserved beside, transmitted special tag is used to indicate source port number. cpu can use this message to judge the incoming port number of the frame. reg 10h.13h.[7] can enable this feature by setting to 1. transmitted special tag (switch ? cpu) 4-byte format: byte 0/1: [15:0] special tag ether-type (default: 0x8086) byte 2: [7:2] reserved [1:0] st_sport, source port number (0~2) byte 3: [7:0] reserved DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 77 DM8603-12-ds-p01 november 8, 2010 9.2.15 priority support the DM8603 supports quality of service (qos) mechanism for multimedia communication such as voip and video conferencing. the DM8603 provides three priority classifications: port-based, 802.1p-based a nd diffserv-based priority. see next section for more detail. the DM8603 offers four level queues for transmit on each port. the DM8603 provides two packet scheduling al gorithms: weighted round robin (wrr) and strict priority queuing (spq). wrr based on their priority and queue weight, the priority weight 8, 4, 2 and 1 for queue 3, 2, 1, and 0 respectively by default. queues with larger weights get more service than smaller. this mechanism can get highly efficient bandwidth and smooth the traffic. strict priority queuing (spq) based on priority only. the packets on the highest priority queu e is transmitted first. the next highest-priority queue is work until last queue empties, and so on. this feature can be set in reg 08h/09h/0ah.17h.[5]. 9.2.15.1 port-based priority port based priority is the simplest scheme and as default. each port has a 2-bit priority value as index for splitting ingress packets to the corresponding transmit queue. this value can be set in reg 08h/09h/0ah.17h.[1:0]. 9.2.15.2 802.1p-based priority the DM8603 extracts 3-bit priority field from rece ived packet with 802.1p vlan tag, and maps this field against vlan priority map registers (reg 10h.17h) to determine which transmit queue is designated. the vlan priority map is programmable. 9.2.15.3 diffserv-based priority diffserv based priority uses the most significant 6- bit of the tos field in standard ipv4 header, and maps this field against tos priority map registers (reg 10h.18h~1fh) to determine which transmit queue is designated. the tos priority map is programmable too. in addition, user can only refer to most significant 3-bit of the tos field optionally, see reg 11h.1eh.[7]. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 78 DM8603-12-ds-p01 november 8, 2010 9.2.16 address table accessing 9.2.16.1 type of address table there are three types of addres s table in the DM8603. the desc ription is represented below: (1). unicast address table this table is used for destination mac address lookup and source mac address learning. the table can have up to 1024 entries. if the table is full, the latest one will kick out the eldest one. the programming method can refer to next section. (2). multicast address table the table that stores multicast addresses shares with unicast address table and can be maintained by host cpu for custom filtering and forwarding multicas t packets. if the table is full, the latest one will kick out the eldest one. all of entri es in multicast address table are stat ic one. in addition to host cpu, multicast address table can be manipulated by in ternal switch engine, if hardware-based igmp snooping function is enabled. (3). igmp membership table this table is used to establish ipv4 multicast forwarding rule under igmp protocol if hardware-based igmp snooping function is enabled. it is automatic maintained by internal engine according to snooping igmp control packets, and can only supp ort to read out by the host cpu. the maximum of entries of table is 16. if the table is full, never join anymore. 9.2.16.2 access rules of address table in DM8603, unicast and multicast address tabl e support ?write?, ?delete?, ?search? and ?read? commands. however, for igmp membership table, t here are only three different type commands such as ?write?, ?delete? and ?read?. the DM8603 procedure an d flow chart of entry access is described as following: z entry write (1). check the busy bit of address table control & status register (reg 15h.10h.[15]) to seek the availability of access engine. waiting until engi ne is available and to keep on following. (2). write the mac address to the address t able data 1~3 registers (reg 15h.12h~14h). (3). write the port number or port map to a ddress table data 0 register (reg 15h.11h.[2:0]). (4). if need, write the entry?s attribute such as static to address table data 4 register (reg 15h.15h.[0]). (5). write the ?write? command and as sign the target table to address table control & status register (reg 15h.10h.[4:0]) to start the operation. (6). check the busy bit again, wait for available. (7). read the command status from address table co ntrol & status register (reg 15h.10h.[14:13]). z entry delete (1). check the busy bit of address table control & status register (reg 15h.10h.[15]) to seek the availability of access engine. waiting until engi ne is available and to keep on following. (2). write the mac address to the address t able data 1~3 registers (reg 15h.12h~14h). (3). write the ?delete? command and assign the ta rget table to address table control & status register (reg 15h.10h.[4:0]) to start the operation. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 79 DM8603-12-ds-p01 november 8, 2010 (4). check the busy bit again, wait for available. (5). read the command status from address table co ntrol & status register (reg 15h.10h.[14:13]). z entry search (1). check the busy bit of address table control & status register (reg 15h.10h.[15]) to seek the availability of access engine. waiting until engi ne is available and to keep on following. (2). write the mac address to the address t able data 1~3 registers (reg 15h.12h~14h). (3). write the ?search? command a nd assign the target table to address table control & status register (reg 15h.10h.[4:0]) to start the operation. (4). check the busy bit again, wait for available. (5). read the command status from address table co ntrol & status register (reg 15h.10h.[14:13]). (6). read the port number or port map to addr ess table data 0 register (reg 15h.11h.[2:0]). (7). if need, read the entry sequence (the sequence number of entry in address table) from address table data 1 register (reg 15h.12h). (8). if need, read the entry?s attributes that include static (unicast address table only) and igmp entry (multicast address table only) from address table data 4 register (reg 15h.15h.[0] for static and reg 15h.15h.[12] for igmp entry). z entry read (1). check the busy bit of address table control & status register (reg 15h.10h.[15]) to seek the availability of access engine. waiting until engi ne is available and to keep on following. (2). write the entry sequence to the addr ess table data 1 register (reg 15h.12h). (3). write the ?read? command and assign the target t able to address table control & status register (reg 15h.10h.[4:0]) to start the operation. (4). check the busy bit again, wait for available. (5). read the command status from address table co ntrol & status register (reg 15h.10h.[14:13]). (6). read the port number or port map to addr ess table data 0 register (reg 15h.11h.[2:0]). (7). if target is unicast or multicast address tabl e, read the entry?s mac a ddress from address table data 1~3 register (reg 15h.12h~14h). if target is igmp membership table, read the real memory address from address table data 1 register (reg 15h.12h.[10:0]). (8). if target is unicast address tabl e, read the entry?s attributes such as static from address table data 4 register (reg 15h.15h.[0]). for multicast address table, igmp entry can be read from address table data 4 register (reg 15h.15h.[12]). for ig mp membership table, igmp valid signal and per-port aged timer can be read from address t able data 2~3 register (reg 15h.13h.[2:0], reg 15h.14h[5:0]). DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 80 DM8603-12-ds-p01 november 8, 2010 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 81 DM8603-12-ds-p01 november 8, 2010 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 82 DM8603-12-ds-p01 november 8, 2010 9.2.17 igmp snooping the internet group management protocol (igmp) is a communications protocol used to manage the membership of internet protocol multicast groups. ig mp is used by ip hosts and adjacent multicast routers to establish multicast group memberships. there are three versions of igmp, as defined by "request for comments" (rfc) documents of the internet engineer ing task force (ietf). igmp v1 is defined by rfc 1112, igmp v2 is defined by rfc 2236 and igmp v3 is defined by rfc 3376. igmp snooping is a feature that allows the switch to "listen in" on the igmp protocol conversation between hosts and routers. the igmp snooping switch hears an igmp report from a host with a given multicast group address. it adds the host's port number to the multicast list for that group, and when the switch hears an igmp leave, it remove s the host's port from the table ent ry. finally, switch will only forward multicast traffic to the hosts interested in that traffic. therefore, this fu nction can effectively reduce multicast traffic. the DM8603 supports igmp v1/v2 snooping and the maxi mal group is 16 without any software effort in this mode. the DM8603 automatically manipulates and updates igmp membership table and multicast table according to igmp control packets, such as membership report and leave. if igmp membership table is full, the later inco ming igmp membership report (join) packet will be ignored and the group address won?t be registered into multicast address table. a fter that, the unregistered ip multicast packets (the destination mac address c an not be found in the multicast address table) will be treated as normal multicast packets by default. the addi tional forwarding control me thod can see the register reg 14h.1bh.[3:2]. the DM8603 supports router ports auto-detect a nd auto-aging mechanism. the port which receives igmp query packets will be treated as r outer port by default. the router port also can be define as static one by user (see reg 14h.1bh.[7]) and the port m ap of the router port can be programmed at reg 14h.1bh.[10:8]. keep in mind that the up port (port 2) is never treated as router port. the DM8603 leaves the router port if the time (router pr esent timeout, 400sec by default) is ex pired that the port never receives igmp query during this period. if receiving v1report or v2report (group join), DM8603 creates new or updates the entry. if receiving leave, DM8603 deletes the ent ry directly when fast leave is enabled, or waiting until timeout. DM8603 removes the entry that was never updated afte r the timer of host timeout (group membership interval) is expired. this timer is programmable in DM8603 and defined by rfc 2236 as ((the robustness variable) times (the query interval)) plus (one query response interval). the setting of the robustness variable and the query interval can see reg 14h.1ch. 9.2.18 ipv6 mld snooping the DM8603 forwards the ipv6 multicast listener discovery (mld) packets to the processor port when mld snooping is enabled and the mld packets meet following scenario: z ipv6 multicast packets. z the hop limit in ipv6 header is 1. z the next header in ipv6 header is 3ah (icmpv6) or 00h (and next header of hop-by-hop option header is 3ah). z the type in icmp header is 82h (multicast listener q uery), 83h (multicast listener report) or 84h (multicast listener done). DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 83 DM8603-12-ds-p01 november 8, 2010 9.2.19 stp / rstp support DM8603 supports both spanning tree protocol (s tp) and rapid spanning tree protocol (rstp). there are five types of stp port state (disabled, blocki ng, listening, learning and forwarding state) and three types of rstp port state (discardi ng, learning and forwarding) for these two protocols. the following figure is the port state diagram of stp. power-on initialization blocking state listening state learning state forwarding state disabled state but in rstp, there are only three port states. the port states comparison between stp and rstp are listed as below. stp port state rstp port state disabled discarding blocking discarding listening discarding learning learning forwarding forwarding for compatibility and design consideration, this function needs the cooperation with external cpu. moreover, the behavior of disabled/blocking/listeni ng states in stp must be equal to the behavior of discarding state in rstp in dm8606. the differe nce between stp and rstp should be implemented by cpu. the following statement describes the stp/rs tp port state behavior and software action in DM8603. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 84 DM8603-12-ds-p01 november 8, 2010 (1). disable state: z drop all packets including bpdus ? implemented by transmitting bpdus to cpu and cpu drops bpdus. z learning is disabled. z does not transmit bpdus received from cpu ? implemented by cpu does not send bpdus to this port (2). blocking state: z drop all packets except bpdus and transmit received bpdus to cpu. z learning is disabled. z does not transmit bpdus received from cpu. (3). listening state: z drop all packets except bpdus an d tranmit received bpdus to cpu z learning is disabled. z forward bpdus received from cpu ? implemented by cpu uses special tag function to send bpdus to decided port. (4). learning state: z drop all packets except bpdus and transmit received bpdus to cpu z learning is enabled z forward bpdus received from cpu (5). forwarding state: z forward all packets z learning is enabled z forward bpdus received from cpu base on the behavior of different states described above, the port states setting of DM8603 for both stp and rstp can see reg 08h/09h/0ah.19h. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 85 DM8603-12-ds-p01 november 8, 2010 the following flow diagram shows ho w to configure stp/rstp function. start set reg 14h.12h.[0] to enable stp/rstp set port states to reg 08h/09h/0ah.19h.[1:0] [1:0] stps0 00: forwarding 01: disabled/discarding 10: learning 11: blocking / listening stp/rstp setting DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 86 DM8603-12-ds-p01 november 8, 2010 9.3 mii interface 9.3.1 mii data interface the DM8603 port 2 provides a media independent interfac e (mii) as defined in the ieee 802.3u standard (clause 22). the mii consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the DM8603 port 2 and ex ternal device (a phy or a mac in reverse mii). ? p2_txd3~0 (transmit data) is a nibble (4 bits) of data that are driven by the DM8603 synchronously with respect to p2_txc. for each p2_txc period, which p2_txe is asserted, p2_txd3~0 are accepted for transmission by the external device. ? p2_txc (transmit clock) from the external devic e is a continuous clock that provides the timing reference for the transfer of the p2_txe, p2_txd3~ 0. the DM8603 can drive 25mhz clock if it is configured to reversed mii mode. ? p2_txe (transmit enable) from the DM8603 port 2 mac indicates that nibbles are being presented on the mii for transmission to the external device. ? p2_rxd3~0 (receive data) is a nibble (4 bits) of data that are sampled by the DM8603 port 2 mac synchronously with respect to p2_rxc. for each p2_rxc period which p2_rxdv is asserted, p2_rxd3~0 are transferred from the external dev ice to the DM8603 port 2 mac reconciliation sub layer. ? p2_rxc3~0 (receive clock) from external device to the DM8603 port 2 mac reconciliation sub layer is a continuous clock that provides the timi ng reference for the transfer of the p2_rxdv, p2_rxd3~0, and p2_rxer signals. ? p2_rxdv (receive data valid) input from the external device to indicates that the external device is presenting recovered and decoded nibbles to the DM8603 port 2 mac reconciliation sub layer. to interpret a receive fram e correctly by t he reconciliation sub layer, p 2_rxdv must encompass the frame, starting no later than t he start-of-frame delimiter and excluding any end-stream delimiter. ? p2_rxer (receive error) input from the external device is synchronously with respect to p2_rxc. p2_rxer will be asserted for 1 or more clock periods to indicate to the reconciliation sub layer that an error was detected somewhere in the frame being transmitted from the external device to the DM8603 port 2 mac. ? p2_crs (carrier sense) is as serted by the external device when either the transmit or receive medium is non-idle, and de-asserted by the exte rnal device when the transmit and receive medium are idle. the p2_crs can also in output mode wh en the DM8603 port 2 is configured to reversed mii mode. ? p2_col (collision detection) is as serted by the external device, when both the transmit and receive medium is non-idle, and de-asserted by the external device when the either transmit or receive medium are idle. the p2_col can also in output mode when the DM8603 port 2 is configured to reversed mii mode. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 87 DM8603-12-ds-p01 november 8, 2010 9.3.2 mii serial management interface the serial control interface uses a simple two-wired se rial interface to obtain and control the status of the physical layer through the mii interface. the serial control interface consists of phy_mdc (management data clock to phy), and phy_mdio (managemen t data input/output to phy) signals. in read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on phy_mdc. the st art of frame delimiter (sfd) is indicated by a <01> pattern followed by the operation code (op) :< 10> indicates read operation and <01> indicates write operation. for read operation, a 2-bit turnaround (ta) filing betw een register address field and data field is provided for phy_mdio to avoid cont ention. following the turnaround time, 16-bit data is read from or written onto management registers. management interface - read frame structure management interface - write frame structure DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 88 DM8603-12-ds-p01 november 8, 2010 9.4 internal phy functions 9.4.1 100base-tx operation the transmitter section contains the following functional blocks: z 4b5b encoder z scrambler z parallel to serial converter z nrz to nrzi converter z nrzi to mlt-3 z mlt-3 driver 9.4.1.1 4b5b encoder the 4b5b encoder converts 4-bit (4b) nibble data gene rated by the mac reconciliation layer into a 5-bit (5b) code group for transmission, see reference table 1. this conversion is required for control and packet data to be combined in code groups. the 4b5b encoder su bstitutes the first 8 bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmit. the 4b5b encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code -groups. at the end of the transmit packet, upon the desertions of the transmit enable signal from the ma c reconciliation layer, the 4b5b encoder injects the t/r code-group pair (01101 00111) indicating the end of frame. after the t/r code -group pair, the 4b5b encoder continuously injects idles into the transmit data stream until transmit enable is asserted and the next transmit packet is detected. 9.4.1.2 scrambler the scrambler is required to control the radiated emissions (emi) by spread ing the transmit energy across the frequency spectrum at the media connec tor and on the twisted pair cable in 100base-tx operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scramble r, energy levels on the cable coul d peak beyond fcc limitations at frequencies related to the repeated 5b sequences, li ke the continuous transmission of idle symbols. the scrambler output is combined with the nrz 5b data fr om the code-group encoder via an xor logic function. the result is a scrambled dat a stream with sufficient randomization to decrease radiated emissions at critical frequencies. 9.4.1.3 parallel to serial converter the parallel to serial converter receives parallel 5b scrambled data from the scrambler, and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi encoder block 9.4.1.4 nrz to nrzi encoder after the transmit data stream has been scramble d and serialized, the data must be nrzi encoded for compatibility with the tp-pmd stand ard, for 100base -tx transmission over category-5 unshielded twisted pair cable. 9.4.1.5 mlt-3 converter the mlt-3 conversion is accomplis hed by converting the data stream output, from the nrzi encoder DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 89 DM8603-12-ds-p01 november 8, 2010 into two binary data streams, with alternately phased logic one event. 9.4.1.6 mlt-3 driver the two binary data streams created at the mlt-3 c onverter are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer?s primary winding, resulting in a minimal current mlt-3 signal. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 90 DM8603-12-ds-p01 november 8, 2010 9.4.1.7 4b5b code group symbol meaning 4b code 3210 5b code 43210 0 data 0 0000 11110 1 data 1 0001 01001 2 data 2 0010 10100 3 data 3 0011 10101 4 data 4 0100 01010 5 data 5 0101 01011 6 data 6 0110 01110 7 data 7 0111 01111 8 data 8 1000 10010 9 data 9 1001 10011 a data a 1010 10110 b data b 1011 10111 c data c 1100 11010 d data d 1101 11011 e data e 1110 11100 f data f 1111 11101 i idle undefined 11111 j sfd (1) 0101 11000 k sfd (2) 0101 10001 t esd (1) undefined 01101 r esd (2) undefined 00111 h error undefined 00100 v invalid undefined 00000 v invalid undefined 00001 v invalid undefined 00010 v invalid undefined 00011 v invalid undefined 00101 v invalid undefined 00110 v invalid undefined 01000 v invalid undefined 01100 v invalid undefined 10000 v invalid undefined 11001 table 1 DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 91 DM8603-12-ds-p01 november 8, 2010 9.4.2 100base-tx receiver the 100base-tx receiver contains several function blocks that convert the scrambled 125mb/s serial data to synchronous 4-bit nibble data. the receive section contains the following functional blocks: z signal detect z digital adaptive equalization z mlt-3 to binary decoder z clock recovery module z nrzi to nrz decoder z serial to parallel z descrambler z code group alignment z 4b5b decoder 9.4.2.1 signal detect the signal detects function meets the specificat ions mandated by the ansi xt12 tp-pmd 100base-tx standards for both voltage thresh olds and timing parameters. 9.4.2.2 adaptive equalization when transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a concern. in high speed twisted pair signali ng, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation, caused by frequenc y variations, must be compensated for to ensure the integrity of the received data. in order to ensure qu ality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cabl e lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation that includes shorte r, less attenuatin g cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. t herefore, the compensation or equalization must be adaptive to ensure proper conditioning of the re ceived signal independent of the cable length. 9.4.2.3 mlt-3 to nrzi decoder the DM8603 decodes the mlt-3 information from th e digital adaptive equalizer into nrzi data. 9.4.2.4 clock recovery module the clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the clock recovery module locks onto the data stream and extracts t he 125 mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 92 DM8603-12-ds-p01 november 8, 2010 9.4.2.5 nrzi to nrz the transmit data stream is required to be nrzi en coded for compatibility with the tp-pmd standard for 100base-tx transmission over category-5 unshielded tw isted pair cable. this conv ersion process must be reversed on the receive end. the nrzi to nrz decode r receives the nrzi data stream from the clock recovery module and converts it to a nrz data stream to be presented to the serial to parallel conversion block. 9.4.2.6 serial to parallel the serial to parallel converter receives a serial data stream from the nrzi to nrz converter. it converts the data stream to parallel dat a to be presented to the descrambler. 9.4.2.7 descrambler because of the scrambling process requires to contro l the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the descramble r receives scrambled parallel data streams from the serial to parallel converter, and it descrambles the data str eams, and presents the data streams to the code group alignment block. 9.4.2.8 code group alignment the code group alignment block receives un-aligned 5b data from the descrambler and converts it into 5b code group data. code group alignment occurs afte r the j/k is detected and subsequent data is aligned on a fixed boundary. 9.4.2.9 4b5b decoder the 4b5b decoder functions as a look-up table that tr anslates incoming 5b code groups into 4b (nibble) data. when receiving a frame, the first 2 5-bit code group s receive the start-of-frame delimiter (j/k symbols). the j/k symbol pair is stripped and two nibbles of pr eamble pattern are substituted. the last two code groups are the end-of-frame delimiter (t/r symbols). the t/r symbol pair is also stripped from the nibble, presented to the reconciliation layer. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 93 DM8603-12-ds-p01 november 8, 2010 9.4.3 10base-t operation the 10base-t transceiver is ieee 802.3u complian t. when the DM8603 is operating in 10base-t mode, the coding scheme is manchester. data processed for tr ansmit is presented in nibble format, converted to a serial bit stream, then the manchester encoded. when receiving, the bit stream, encoded by the manchester, is decoded and converted into nibble format. 9.4.4 collision detection for half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. collision detection is disabled in full duplex operation. 9.4.5 carrier sense carrier sense (crs) is asserted in half-duplex operation during transmis sion or reception of data. during full-duplex mode, crs is asserted only during receive operations. 9.4.6 auto-negotiation the objective of auto-negotiation is to provide a means to exchange information between linked devices and to automatically configure both devices to take maxi mum advantage of their abilities. it is important to note that auto-negotiation does not test the characte ristics of the linked segment. the auto-negotiation function provides a means for a device to advertise s upported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. this allows devices on both ends of a s egment to establish a link at the best common mode of operation. if more than one common mode exists bet ween the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operat ion using a predetermined priority resolution function. auto-negotiation also provides a parallel detection function for devices that do not support the auto-negotiation feature. during parallel detection t here is no exchange of information of configuration. instead, the receive signal is examined. if it is disco vered that the signal matches a technology, which the receiving device supports, a connection will be automatica lly established using that technology. this allows devices not to support auto-negotiation but suppor t a common mode of operation to establish a link. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 94 DM8603-12-ds-p01 november 8, 2010 9.5 lfp and fef function the DM8603 pairs port 0 and port 1 for media conv erter application and supports lfp (link fault pass-through) and fef (far end fault) troubleshooting features. the lfp (link fault pass-through) allows the DM8603 to monitor both the fiber and tp ports for loss of signal. in case of a loss of rx signal on one media port, the DM8603 will automatica lly disable the tx signal to t he other media port, thus passing through the link fault. fef (far end fault) enables the DM8603 to stop sending link pulse to the link partner once a loss of the fiber rx signal is encountered. then the link partner will synchronously stop sending data. fef prevents loss of valuable data transmitted over invalid link. combining those two function of DM8603, both end devices can be notified of a loss of fiber link. 9.6 hp auto-mdix function the DM8603 supports the automatic detect cable co nnection type, mdi/mdix (straight through/cross over). a manual configuration by register bit for mdi or mdix is still accepted. when set to automatic, the polarity of mdi/mdix cont rolled timing is generated by 16-bits lfsr. the switching cycle time is located from 200ms to 420ms . the polarity control is always switch until detect received signal. after selected mdi or mdix, this feature is able to detect the required cable connection type. (straight through or crossed over) and make correction automatically rx + /- from DM8603 rx+/- to rj45 tx + /- from DM8603 tx+/-to rj45 * mdi: __________ * mdix: - - - - - - - - - DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 95 DM8603-12-ds-p01 november 8, 2010 10. dc and ac electrical characteristics 10.1 absolute maximum ratings symbol parameter min. max. unit conditions dvdd33 digital 3.3v power -0.3 3.6 v dvdd18 digital 1.8v power -0.3 1.95 v avdd33 analog 3.3v power -0.3 3.6 v avdd18 analog 1.8v power -0.3 1.95 v iov input/output voltage -0.5 5.5 v t stg storage temperature range -65 +150 c t a ambient temperature 0 +70 c l t lead temperature (tl, soldering, 10 sec.). - +260 c 10.2 operating conditions symbol parameter min. typ. max. unit conditions dvdd33 digital 3.3v power 3.135 - 3.465 v - dvdd18 digital 1.8v power 1.71 - 1.89 v - avdd33 analog 3.3v power 3.135 - 3.465 v - avdd18 analog 1.8v power 1.71 - 1.89 v - - 107 - ma 1.8v only 100base-tx - 54 - ma 3.3v only - 57 - ma tx idle, 1.8v only - 64 - ma 100% utilization, 1.8v only p d (power dissipation) 10base-tx - 11 - ma 3.3v only DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 96 DM8603-12-ds-p01 november 8, 2010 10.3 dc electrical characteristics symbol parameter min. typ. max. unit conditions inputs vil input low voltage - - 0.8 v vcond1* vih input high voltage 2.0 - - v vcond1 iil input low leakage current -1 - - ua vin = 0.0v, vcond1 iih input high leakage current - - 1 ua vin = 3.3v, vcond1 outputs vol output low voltage - - 0.4 v iol = 4ma voh output high voltage 2.4 - - v ioh = -4ma receiver vicm rx+/rx- common mode input voltage - 1.8 - v 100 termination across transmitter vtd100 100tx+/- differential output voltage 1.9 2.0 2.1 v peak to peak vtd10 10tx+/- differential output voltage 4.4 5 5.6 v peak to peak itd100 100tx+/- differential output current 19 20 21 ma absolute value itd10 10tx+/- differential output current 44 50 56 ma absolute value note: 1. vcond1: dvdd33 = 3.3v, dvdd18 = 1.8v, avdd33 = 3.3v, avdd18 = 1.8v. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 97 DM8603-12-ds-p01 november 8, 2010 10.4 ac characteristics 10.4.1 power on reset timing symbol parameter min. typ. max. unit conditions t1 pwrst# low period 1 - - ms - t2 strap pin hold time with pwrst# 40 - - ns - t3 pwrst# high to eecs high - 5 - us t4 pwrst# high to eecs burst end - -- 4 ms DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 98 DM8603-12-ds-p01 november 8, 2010 10.4.2 port 2 mii interface transmit timing symbol parameter min. typ. max. unit t1 100m mii transmit clock period - 40 - ns t1 10m mii transmit clock period - 400 - ns t2 p2_txe,p2_txd3~0 to p2_txc rising output delay 8 ns 10.4.3 port 2 mii interface receive timing symbol parameter min. typ. max. unit t1 100m mii receive clock period - 40 - ns t1 10m mii receive clock period - 400 - ns t2 p2_rxer, p2_rxdv and p2_rxd3~0 to p2_rxc setup time 5 - - ns t3 p2_rxer, p2_rxdv and p2_rxd3~0 to p2_rxc hold time 5 - - ns DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 99 DM8603-12-ds-p01 november 8, 2010 10.4.4 port 2 rmii interface transmit timing symbol parameter min. typ. max. unit t1 rmii ref_clk period - 20 - ns t2 p2_txe,p2_txd1~0 to ref_clk rising output delay 8 ns 10.4.5 port 2 rmii interface receive timing symbol parameter min. typ. max. unit t1 rmii ref_clk period - 20 - ns t2 crs_dv, p2_rxd to ref_clk setup time 4 - - ns t3 crs_dv, p2_rxd1~0 to ref_clk hold time 2 - - ns DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 100 DM8603-12-ds-p01 november 8, 2010 10.4.6 mii management interface timing symbol parameter min. typ. max. unit t1 phy_mdc period - 1920 - ns t2 phy_mdio to phy_mdc setup time on input state 40 - - ns t3 phy_mdio to phy_mdc hold time on input state 40 - - ns t4 phy_mdio to phy_mdc rising output delay on output state - 960 - ns 10.4.7 host smi interface timing symbol parameter min. typ. max. unit t1 smi_mdc period 80 - - ns t2 smi_mdio to smi_mdc setup time on input state 40 - - ns t3 smi_mdio to smi_mdc hold time on input state 40 - - ns t4 smi_mdio to smi_mdc rising output delay on output state - 5 - ns DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 101 DM8603-12-ds-p01 november 8, 2010 10.4.8 eeprom timing symbol parameter min. typ. max. unit t1 eeck period - 5120 - ns t2 eecs to eeck rising output delay - 4160 - ns t3 eedio to eeck rising output delay on output state - 4160 - ns t4 eedio to eeck rising setup time on input state 8 - - ns t5 eedio to eeck rising hold time on input state 8 - - ns DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 102 DM8603-12-ds-p01 november 8, 2010 11. application information 11.1 application of reverse mii phy_mdc phy_mdio p2_rxc p2_txe p2_crs p2_rxd3~0 p2_rxer p2_txer revmii mac i/f DM8603 txd[3:0] txen rxdv crs col mii mac i/f nc nc rxer p2_txd3~0 p2_txc p2_rxdv p2_col txclk rxclk rxd[3:0] nc nc smi_mdc smi_mdio mdc mdio note: the p2_txe and p2_txd2 pins of DM8603 must be pull-up resistor with 4.7k ohm to dvdd33 in this application. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 103 DM8603-12-ds-p01 november 8, 2010 11.2 application of reduce mii to phy phy_mdc phy_mdio p2_txd1~0 p2_txe p2_crs p2_rxd1~0 p2_rxc p2_txc rmii mac i/f mdc mdio txd[1:0] tx_en crs_dv rxd[1:0] ref_clk rmii phy i/f 50 mhz reference clock smi_mdc smi_mdio nc nc nc rx_er* nc note: the p2_txd3 pin of DM8603 must be pull-up resistor with 4.7k ohm to dvdd33 in this application. 11.3 application of reduce mii to mac phy_mdc phy_mdio p2_txd1~0 p2_txe p2_crs p2_rxd1~0 p2_rxc p2_txc rmii mac i/f rxd[1:0] crs_dv tx_en txd[1:0] ref_clk rmii mac i/f 50 mhz reference clock nc nc smi_mdc smi_mdio mdc mdio rx_er note: the p2_txe and p2_txd3 pins of DM8603 must be pull-up resistor with 4.7k ohm to dvdd33 in this application. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 104 DM8603-12-ds-p01 november 8, 2010 12. package information 64 pins lqfp package outline information: dimension in mm dimension in inch symbol min nom max min nom max a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b 1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 - 0.20 0.004 - 0.008 c 1 0.09 - 0.16 0.004 - 0.006 d 12.00 bsc 0.472 bsc d 1 10.00 bsc 0.394 bsc e 12.00 bsc 0.472 bsc e 1 10.00 bsc 0.394 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0.018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 - - 0.003 - - r 2 0.08 - 0.20 0.003 - 0.008 s 0.20 - - 0.008 - - 0 o 3.5 o 7 o 0 o 3.5 o 7 o 1 0 o - - 0 o - - 2 12 o typ 12 o typ 3 12 o typ 12 o typ 1. dimension d 1 and e 1 do not include resin fin. 2. all dimensions are base on metric system. 3. general appearance spec should base on its final visual inspection spec. DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 105 DM8603-12-ds-p01 november 8, 2010 13. terminology b bist built-in self-test bpdu bridge protocol data unit byte 8-bits c cfi canonical format indicator col collision crc cyclic redundancy check crs carrier sense csr control and status registers d dmac destination mac address e esd end of stream delimiter f fef far end fault flp fast link pulse h host external system (includes proc essor, application software, etc.) i igmp internet group management protocol ipg inter-packet gap l lfp link fault pass-through lqfp low-profile quad flat package m mac media access controller mdi medium dependant interface mdix media independent interface with crossover mii media independent interface mib management information base mld multicast listener discovery mlt-3 multi-level transmission encoding (3-levels) n nrzi non return to zero inverter nrz non return to zero o oui organizationally unique identifier p phy physical layer pmd physical medium dependent pvid port vid q qinq ieee 802.1q-in-q vlan tag, double-tagged DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 106 DM8603-12-ds-p01 november 8, 2010 qos quality of service r reg register revmii reversed mii rmii reduce mii rstp ieee 802.1w - rapid spanning tree protocol s sfd start of frame delimiter smac source mac address smi serial management interface stp ieee 802.1d - spanning tree protocol t tos type of service tp twisted pair v vid vlan identifier vlan virtual lan w word 16-bits DM8603 10/100 mbps 3-port ethernet switch controller with mii / rmii interface preliminary datasheet 107 DM8603-12-ds-p01 november 8, 2010 14. ordering information part number pin count package DM8603ep 64 lqfp (pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirements, e. g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writi ng. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applicatio ns. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based park, hsin-chu city, taiwan, r.o.c. tel: +886-3-5798797 fax: +886-3-5646929 mail: sales@davicom.com.tw http: http://www.davicom.com.tw warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/o r function. |
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